JPH04253348A - Method for connecting lsi chip - Google Patents
Method for connecting lsi chipInfo
- Publication number
- JPH04253348A JPH04253348A JP9127891A JP2789191A JPH04253348A JP H04253348 A JPH04253348 A JP H04253348A JP 9127891 A JP9127891 A JP 9127891A JP 2789191 A JP2789191 A JP 2789191A JP H04253348 A JPH04253348 A JP H04253348A
- Authority
- JP
- Japan
- Prior art keywords
- lsi chip
- substrate
- electrode
- resin
- electrode terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、LSIチップ等の微細
な電極と実装基板上に設けた電極との接続実装に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to connection and mounting between fine electrodes such as LSI chips and electrodes provided on a mounting board.
【0002】0002
【従来の技術】従来、この種の電気接続用異方性導電材
料としては、高分子材料の表面に導電性を有する金属薄
層を形成した導電粒子を含んだ接着剤組成物が用いられ
ており、接続としては、180〜200℃で20〜30
kg/cm2程度の熱圧着方法が用いられていた。[Prior Art] Conventionally, as this type of anisotropic conductive material for electrical connection, an adhesive composition containing conductive particles forming a conductive metal thin layer on the surface of a polymeric material has been used. The connection temperature is 20-30℃ at 180-200℃.
A thermocompression bonding method of approximately kg/cm2 was used.
【0003】以下に従来の実装方法を説明する。図3は
、従来のLSIチップの接続方法を工程順に示す基板の
断面図である。このLSIチップの接続は、次のとおり
である。すなわち、図3(a)に示すように、電極パッ
ド2が形成されたLSIチップ1と、電極パッド2に対
応して形成された電極端子4を有する基板3とを導電性
粒子9を分散させて含有している熱接着樹脂11を介し
て向き合わせる。次に、図3(b)に示すように、LS
Iチップ1を基板3とに押し付け、加熱することにより
、熱接着樹脂11を軟化させ、電極パッド2と電極端子
4とを導電性粒子9により、接続することによって行わ
れる。A conventional mounting method will be explained below. FIG. 3 is a cross-sectional view of a substrate showing a conventional LSI chip connection method in the order of steps. The connections of this LSI chip are as follows. That is, as shown in FIG. 3(a), an LSI chip 1 having electrode pads 2 formed thereon and a substrate 3 having electrode terminals 4 formed corresponding to the electrode pads 2 are separated by dispersing conductive particles 9. They face each other with a thermal adhesive resin 11 contained therebetween. Next, as shown in FIG. 3(b), LS
The I-chip 1 is pressed against the substrate 3 and heated to soften the thermal adhesive resin 11, and the electrode pads 2 and the electrode terminals 4 are connected by the conductive particles 9.
【0004】0004
【発明が解決しようとする課題】上述した従来の接続実
装方法によれば、電極パッドと電極端子間を電気的に接
続している導電性粒子の数量が多くなると隣合う電極パ
ッド、あるいは電極端子間でショートあるいは電流リー
クが発生する。これを避けるために導電性粒子の数量を
少なくすると、接続抵抗が増大すると共にばらつくとい
う問題が発生していた。また甚だしい場合には電気的に
オープンになる接続箇所が発生していた。さらに、最近
の接続寸法の高精細化に伴って、この傾向はますます著
しくなっている。また、LSIチップと基板が厳密に平
行なまま押し付けることは極めて難しく、各々の電極端
子間のギャップにばらつきが発生し、各電極端子間の導
電粒子の数量にばらつきが生じ、結果として接続が不安
定になるという問題があった。これらの現象は、デバイ
スの動作不良を引き起こす重大な欠点となっている。[Problems to be Solved by the Invention] According to the conventional connection and mounting method described above, when the number of conductive particles electrically connecting an electrode pad and an electrode terminal increases, the adjacent electrode pad or electrode terminal A short circuit or current leak occurs between the two. If the number of conductive particles is reduced in order to avoid this, the problem arises that the connection resistance increases and varies. Furthermore, in extreme cases, some connections may become electrically open. Furthermore, this trend is becoming more and more noticeable as the connection dimensions have become increasingly finer in recent years. In addition, it is extremely difficult to press the LSI chip and the substrate while keeping them strictly parallel, which causes variations in the gap between each electrode terminal, and variations in the number of conductive particles between each electrode terminal, resulting in poor connection. There was a problem with stability. These phenomena are serious drawbacks that cause device malfunctions.
【0005】本発明の目的は、再現性が良く、安定で、
しかも高精細化が可能なLSIチップの接続方法を提供
することにある。[0005] The object of the present invention is to have good reproducibility, stability,
Moreover, it is an object of the present invention to provide a method for connecting LSI chips that can achieve high definition.
【0006】[0006]
【課題を解決するための手段】上記目的を達成するため
、本発明による接続実装方法においては、LSIチップ
に形成された電極パッドと、該電極パッドに対応して基
板に形成された電極端子とを接続するLSIチップの接
続方法であって、前記LSIチップあるいは、基板表面
の一方に活性エネルギー線による硬化及び熱硬化性を有
する樹脂中に導電性粒子を分散させた溶液を塗布後、乾
燥する工程と、前記導電性粒子を分散させた溶液を塗布
していない基板表面あるいは、LSIチップの一方に活
性エネルギー線による硬化及び熱硬化性を有する樹脂を
塗布後、乾燥する工程と、前記LSIチップ及び、基板
表面の接着剤樹脂をリソグラフィー及び現像により除去
する工程と、前記電極パッドと電極端子とを向き合わせ
、半導体回路素子と基板間を密着後、熱圧着して硬化さ
せる工程とを含むものである。[Means for Solving the Problems] In order to achieve the above object, in the connection mounting method according to the present invention, electrode pads formed on an LSI chip and electrode terminals formed on a substrate corresponding to the electrode pads are provided. A method for connecting an LSI chip, which involves applying a solution of conductive particles dispersed in a thermosetting resin that is cured by active energy rays to one of the surfaces of the LSI chip or the substrate, and then dried. a step of applying a thermosetting resin that is cured by active energy rays to the surface of the substrate or one side of the LSI chip on which the solution in which the conductive particles are dispersed is not applied, and then drying the LSI chip; and a step of removing the adhesive resin on the surface of the substrate by lithography and development, and a step of facing the electrode pad and the electrode terminal, closely bonding the semiconductor circuit element and the substrate, and then curing by thermocompression bonding. .
【0007】[0007]
【作用】再現性が良く、安定で、接続信頼性が高く、し
かも高精細化が可能となる。[Function] Good reproducibility, stability, high connection reliability, and high definition.
【0008】[0008]
【実施例】次に、本発明について図面を参照して説明す
る。図1A,図1Bは、本発明の一実施例としてLSI
チップの接続方法を工程順に示す断面図である。図2は
、本発明方法によって接続されたLSIチップの断面図
である。まず図1Aの(a)に示すように、LSIチッ
プ1の表面には、電極パッド2が形成され、一方基板3
には、電極パッド2に対応して電極端子4が形成されて
いる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. 1A and 1B show an LSI as an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a method for connecting chips in order of steps. FIG. 2 is a cross-sectional view of an LSI chip connected by the method of the present invention. First, as shown in FIG. 1A (a), electrode pads 2 are formed on the surface of an LSI chip 1, and a substrate 3 is formed on the surface of an LSI chip 1.
Electrode terminals 4 are formed in correspondence with the electrode pads 2.
【0009】本発明においては、図1Aの(b)に示す
ように、LSIチップ1上に、光硬化性と同時に熱硬化
性を有する樹脂をスピンナー等で均一に塗布後、乾燥す
る。次に、フォトリソグラフィーにより紫外線7露光を
行う。このとき、電極パッド2上の樹脂層を遮光して露
光を行う。図1Aの(c)に示すように、基板3上に、
光硬化性と同時に熱硬化性を有する樹脂中に導電性粒子
を分散させた溶液をスピンナー等で均一に塗布後、乾燥
する。次に、フォトリソグラフィーにより紫外線7露光
を行う。このとき、電極端子4の樹脂層の露光を行う。
実施例では、感光性基(ネガ型)を有したポリイミド前
駆体である旭化成工業株式会社製「パイメル」(商品名
)を用い、導電性粒子としては、積水ファインケミカル
株式会社製「ミクロパール」(商品名)を用いた。次に
、図1Bの(d)に示すように、現像液10にて現像を
行い、LSIチップ及び基板3上の樹脂層を除去しマス
クパターンを作成する。次に図1Bの(e)に示すよう
に、電極パッド2と電極端子4とを向き合わせる。In the present invention, as shown in FIG. 1A (b), a resin having both photocurability and thermosetting properties is uniformly applied onto the LSI chip 1 using a spinner or the like, and then dried. Next, UV 7 exposure is performed by photolithography. At this time, exposure is performed while shielding the resin layer on the electrode pad 2 from light. As shown in FIG. 1A (c), on the substrate 3,
A solution in which conductive particles are dispersed in a resin that has both photocurability and thermosetting properties is uniformly applied using a spinner or the like, and then dried. Next, UV 7 exposure is performed by photolithography. At this time, the resin layer of the electrode terminal 4 is exposed. In the examples, "Pimel" (trade name) manufactured by Asahi Kasei Corporation, which is a polyimide precursor having a photosensitive group (negative type), was used, and as the conductive particles, "Micro Pearl" (manufactured by Sekisui Fine Chemical Co., Ltd.) was used. (product name) was used. Next, as shown in FIG. 1B (d), development is performed using a developer 10 to remove the resin layer on the LSI chip and the substrate 3 to create a mask pattern. Next, as shown in FIG. 1B (e), the electrode pad 2 and the electrode terminal 4 are faced to each other.
【0010】次に、電極パッド2と電極端子4とを向き
合わせLSIチップ1を基板3上に乗せ、電極パッド2
と電極端子4とをよく密着させる。さらに、10kg/
cm2程度荷重を加えてLSIチップ1を圧下し、同時
に250℃程度に加熱することによって、LSIチップ
と基板3間に配した樹脂を硬化させ、図2のようにLS
Iチップ1と基板3を接着固定する。Next, the LSI chip 1 is placed on the substrate 3 with the electrode pads 2 and electrode terminals 4 facing each other, and the electrode pads 2 and 4 are placed facing each other.
and the electrode terminal 4 are brought into close contact with each other. Furthermore, 10kg/
By pressing down the LSI chip 1 by applying a load of about cm2 and simultaneously heating it to about 250°C, the resin placed between the LSI chip and the substrate 3 is cured, and the LS
The I-chip 1 and the substrate 3 are bonded and fixed.
【0011】なお、感光性と熱硬化性を有する樹脂を基
板3に、感光性と熱硬化性を有する樹脂中に導電性粒子
を分散させた溶液をLSIチップ1に塗布し、以下、工
程順に従って接続を行ってもよい。[0011] A photosensitive and thermosetting resin is applied to the substrate 3, and a solution in which conductive particles are dispersed in the photosensitive and thermosetting resin is applied to the LSI chip 1. The connection may be made according to the following.
【0012】0012
【発明の効果】以上説明したように、本発明のLSIチ
ップの接続方法は、リソグラフィー技術により電極パッ
ドと電極端子間のみに導電性粒子を分散させた接着剤層
を配し、さらに絶縁部分はリソグラフィー技術により、
導電性粒子を含まない接着剤層を配して熱圧着接続され
ているので高精細化接続が確実に、容易に信頼性よく実
施できるという極めて顕著な効果が得られる。As explained above, in the LSI chip connection method of the present invention, an adhesive layer in which conductive particles are dispersed is disposed only between the electrode pad and the electrode terminal using lithography technology, and the insulating part is With lithography technology,
Since the adhesive layer containing no conductive particles is arranged and the connection is made by thermocompression, a very remarkable effect can be obtained in that high-definition connection can be reliably, easily and reliably performed.
【図1A】本発明に係わるLSIチップの接続方法の工
程の前段を工程順に示す断面図である。FIG. 1A is a cross-sectional view showing the first stage of the LSI chip connection method according to the present invention in the order of steps;
【図1B】本発明に係わるLSIチップの接続方法の工
程の後段を工程順に示す断面図である。FIG. 1B is a cross-sectional view showing the latter stages of the LSI chip connection method according to the present invention in the order of steps.
【図2】本発明方法により接続されたLSIチップの断
面図である。FIG. 2 is a cross-sectional view of an LSI chip connected by the method of the present invention.
【図3】従来のLSIチップの接続方法を工程順に示す
断面図である。FIG. 3 is a cross-sectional view showing a conventional LSI chip connection method in the order of steps.
1 LSIチップ
2 電極パッド
3 基板
4 電極端子
5 感光性と熱硬化性を有する樹脂
6 フォトマスク
7 紫外線
8 導電性粒子を分散させた光と熱硬化性を有する樹
脂9 導電性粒子
10 現像液
11 熱接着樹脂1 LSI chip 2 Electrode pad 3 Substrate 4 Electrode terminal 5 Photosensitive and thermosetting resin 6 Photomask 7 Ultraviolet light 8 Light and thermosetting resin 9 containing conductive particles dispersed therein Conductive particles 10 Developing solution 11 thermal adhesive resin
Claims (1)
と、該電極パッドに対応して基板に形成された電極端子
とを接続するLSIチップの接続方法であって、前記L
SIチップあるいは、基板表面の一方に活性エネルギー
線による硬化及び熱硬化性を有する樹脂中に導電性粒子
を分散させた溶液を塗布後、乾燥する工程と、前記導電
性粒子を分散させた溶液を塗布していない基板表面ある
いは、LSIチップの一方に活性エネルギー線による硬
化及び熱硬化性を有する樹脂を塗布後、乾燥する工程と
、前記LSIチップ及び、基板表面の接着剤樹脂をリソ
グラフィー及び現像により除去する工程と、前記電極パ
ッドと電極端子とを向き合わせ、半導体回路素子と基板
間を密着後、熱圧着して硬化させる工程とを含むことを
特徴とするLSIチップの接続方法。1. An LSI chip connection method for connecting an electrode pad formed on an LSI chip and an electrode terminal formed on a substrate corresponding to the electrode pad, the method comprising:
A step of coating one of the surfaces of the SI chip or the substrate with a solution in which conductive particles are dispersed in a thermosetting resin that is cured by active energy rays, and then drying the solution; A step of coating the uncoated surface of the substrate or one of the LSI chips with a resin that is cured by active energy rays and having thermosetting properties, and then drying the surface, and applying the adhesive resin on the LSI chip and the surface of the substrate by lithography and development. A method for connecting an LSI chip, comprising the steps of: removing the electrode pads and electrode terminals, bringing the semiconductor circuit element and the substrate into close contact with each other, and then thermocompression bonding and curing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3027891A JP2661382B2 (en) | 1991-01-29 | 1991-01-29 | LSI chip connection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3027891A JP2661382B2 (en) | 1991-01-29 | 1991-01-29 | LSI chip connection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04253348A true JPH04253348A (en) | 1992-09-09 |
| JP2661382B2 JP2661382B2 (en) | 1997-10-08 |
Family
ID=12233517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3027891A Expired - Lifetime JP2661382B2 (en) | 1991-01-29 | 1991-01-29 | LSI chip connection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2661382B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5381047A (en) * | 1992-05-27 | 1995-01-10 | Kanno; Kazumasa | Semiconductor integrated circuit having multiple silicon chips |
| US5838061A (en) * | 1996-03-11 | 1998-11-17 | Lg Semicon Co., Ltd. | Semiconductor package including a semiconductor chip adhesively bonded thereto |
| CN110098167A (en) * | 2018-01-31 | 2019-08-06 | 三国电子有限会社 | The production method of connection structural bodies and connection structural bodies |
| US11735556B2 (en) | 2018-01-31 | 2023-08-22 | Mikuni Electron Corporation | Connection structure |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3451987B2 (en) | 1998-07-01 | 2003-09-29 | 日本電気株式会社 | Functional element, substrate for mounting functional element, and method of connecting them |
-
1991
- 1991-01-29 JP JP3027891A patent/JP2661382B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5381047A (en) * | 1992-05-27 | 1995-01-10 | Kanno; Kazumasa | Semiconductor integrated circuit having multiple silicon chips |
| US5838061A (en) * | 1996-03-11 | 1998-11-17 | Lg Semicon Co., Ltd. | Semiconductor package including a semiconductor chip adhesively bonded thereto |
| CN110098167A (en) * | 2018-01-31 | 2019-08-06 | 三国电子有限会社 | The production method of connection structural bodies and connection structural bodies |
| JP2019134085A (en) * | 2018-01-31 | 2019-08-08 | 三国電子有限会社 | Connection structure and manufacturing method thereof |
| US11735556B2 (en) | 2018-01-31 | 2023-08-22 | Mikuni Electron Corporation | Connection structure |
| CN110098167B (en) * | 2018-01-31 | 2024-12-31 | 三国电子有限会社 | Connecting structure and method for manufacturing connecting structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2661382B2 (en) | 1997-10-08 |
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