JPH04256351A - Ic package - Google Patents

Ic package

Info

Publication number
JPH04256351A
JPH04256351A JP3017231A JP1723191A JPH04256351A JP H04256351 A JPH04256351 A JP H04256351A JP 3017231 A JP3017231 A JP 3017231A JP 1723191 A JP1723191 A JP 1723191A JP H04256351 A JPH04256351 A JP H04256351A
Authority
JP
Japan
Prior art keywords
printed
circuit board
upward
package
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3017231A
Other languages
Japanese (ja)
Inventor
Masahiro Arai
雅裕 新井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3017231A priority Critical patent/JPH04256351A/en
Publication of JPH04256351A publication Critical patent/JPH04256351A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To simply wire printed patterns on a printed-circuit board in the double-sided surface mounting operation of an IC by a method wherein a lead frame for the IC is arranged so as to be common for the upper part and the lower part of the IC and the IC can be mounted so as to be faced both upward and downward. CONSTITUTION:In order to simply wire printed patterns on a printed-circuit board at the double-sided surface mounting operation of IC's 11, 12, lead frames 1 for the IC's 11, 12 are arranged so as to be common for the upper part and the lower part of the IC's 11, 12 so that the IC's 11, 12 can be mounted so as to be faced both upward and downward. For example, lead frames 1 are extracted from the lower part of an IC, they are turned down upward along side faces of a sealed resin 2 and they are turned down further at the upper part. Thereby, an IC 1 is mounted at the upper part of a printed-circuit board 14 and an IC 2 is mounted at the lower part in such a way that their positions are lined up and that faces A's of the IC's are faced upward. In this case, pins for the IC's at the upper part and the lower part at the printed-circuit board 14 are arranged to be common. Consequently, printed patterns can be wired simply at the double-sided surface mounting operation of an IC package.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明はＩＣパッケージに関する
。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to IC packages.

【０００２】0002

【従来の技術】従来、この種の両面面実装可能なタイプ
のＩＣのパッケージにはＳＯＰ（Ｓｍａｌｌ　　Ｏｕｔ
ｌｉｎｅ　　Ｐａｃｋａｇｅ），ＳＯＪ（ＳｍａｌｌＯ
ｕｔｌｉｎｅ　　Ｊ−ｌｅａｄｅｄ　　Ｐａｆｋａｇｅ
），ＬＣＣ（Ｌｅａｄｌｅｓｓ　　Ｃｈｉｐ　　Ｃａｒ
ｒｉｅｒ）等のタイプのパッケージの種類があった。図
３は従来の一例を示す上面図である。図３に示すＩＣを
両面実装するには、図４に示すような配線パターンをプ
リント基板の両面に設けていた。[Prior Art] Conventionally, this type of IC package that can be mounted on both sides has a SOP (Small Out).
line Package), SOJ(SmallO
utline J-leaded Pafkage
), LCC (Leadless Chip Car
There were various types of packages such as FIG. 3 is a top view showing a conventional example. In order to mount the IC shown in FIG. 3 on both sides, wiring patterns as shown in FIG. 4 were provided on both sides of the printed circuit board.

【０００３】0003

【発明が解決しようとする課題】従来のＩＣパッケージ
は、両面面実装をした場合、ＤＲＡＭ（Ｄｙｎａｍｉｃ
Ｒａｎｄｏｍ　　Ａｃｃｅｓｓ　　Ｍｅｍｏｒｙ）を例
に取ると、ＲＡＳバー，ＣＡＳバー，アドレス等の信号
が表面，裏面で共通化している場合においても、両面に
パターンを走らせる必要があるという欠点がった。[Problems to be Solved by the Invention] When a conventional IC package is mounted on both sides, DRAM (Dynamic
Taking Random Access Memory (Random Access Memory) as an example, even when signals such as RAS bar, CAS bar, address, etc. are shared on the front and back sides, the pattern has to be run on both sides, which is a drawback.

【０００４】0004

【課題を解決するための手段】本発明のＩＣパッケージ
は、ＩＣ自体を両面実装させるために、ＩＣの上部およ
び下部に共通にリードフレームを有する構造を持つ。[Means for Solving the Problems] The IC package of the present invention has a structure in which a lead frame is commonly provided at the upper and lower parts of the IC so that the IC itself can be mounted on both sides.

【０００５】[0005]

【実施例】次に本発明について図面を参照して説明する
。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

【０００６】図１は本発明の一実施例の模式図である。 ダイパッド５上のチップ４の入出力信号はボンディング
ワイヤー３でリードフレーム１と電気的に結合され、樹
脂２で封止されている。ＩＣを上向きでも下向きにも実
装させるためにリードフレーム１をＩＣの下部より引き
出し、封止した樹脂２の側面に沿って上へ折り返し、さ
らに上部で折り返す。FIG. 1 is a schematic diagram of an embodiment of the present invention. Input/output signals of the chip 4 on the die pad 5 are electrically coupled to the lead frame 1 through bonding wires 3 and sealed with a resin 2. In order to mount the IC either upward or downward, the lead frame 1 is pulled out from the bottom of the IC, folded upward along the side of the sealed resin 2, and further folded back at the top.

【０００７】これにより本発明のＩＣを両面面実装する
場合、図２のＩＣパッケージの実装例に示す様にプリン
ト基板１４の上部にＩＣ１，下部にＩＣ２をそれぞれ位
置をそろえＩＣのＡ面（チップ側をＡ面，ダイパッド側
をＢ面とする）を上にして実装した場合、プリント基板
の上下のＩＣのピン配置は共通となる。プリント基板の
表裏で共通化できる信号があれば、その信号ピンのパッ
ド１６をスルーホール１３にすればプリントパターン配
線は片面で済む事になる。Accordingly, when the IC of the present invention is mounted on both sides, as shown in the mounting example of an IC package in FIG. When the ICs are mounted with the side facing up (the A side is the A side and the die pad side is the B side), the pin arrangement of the ICs on the top and bottom of the printed circuit board will be the same. If there is a signal that can be shared between the front and back sides of the printed circuit board, if the pad 16 of the signal pin is made into a through hole 13, the printed pattern wiring can be done on one side.

【０００８】図３に示したＤＲＡＭのモデルを両面面実
装する場合、プリント基板１４の片面に図４に示す様な
プリントパターンを施し、アドレス，ＲＡＳバー，ＣＡ
Ｓバー，ＷＥバー，ＧＮＤ，ＶＣＣは共通であるので、
これらの部分のパッドをスルーホールにすると、もう一
方の面のこれらの信号のプリントパターンの配線が不要
になる。When mounting the DRAM model shown in FIG. 3 on both sides, a printed pattern as shown in FIG. 4 is applied to one side of the printed circuit board 14, and addresses, RAS bars, CA
Since S bar, WE bar, GND, and VCC are common,
If the pads in these areas are made into through holes, wiring of the printed pattern for these signals on the other side becomes unnecessary.

【０００９】[0009]

【発明の効果】本発明のＩＣパッケージを両面面実装時
に用いると、プリントパターン配線の簡略化が計れる。Effects of the Invention When the IC package of the present invention is used for double-sided surface mounting, printed pattern wiring can be simplified.

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】本発明の一実施例を示す模式図である。FIG. 1 is a schematic diagram showing an embodiment of the present invention.

【図２】図１に示すＩＣパッケージの一使用例を示す側
面図である。FIG. 2 is a side view showing an example of use of the IC package shown in FIG. 1;

【図３】従来の一例を示す上面図である。FIG. 3 is a top view showing a conventional example.

【図４】図３に示すＩＣパッケーシの一使用例の動作を
説明するためのパターン図である。FIG. 4 is a pattern diagram for explaining the operation of one usage example of the IC package shown in FIG. 3;

【符号の説明】[Explanation of symbols]

１　　　　リードフレーム ２　　　　樹脂 ３　　　　ボンディングワイヤ ４　　　　チップ ５　　　　ダイパッド 1 Lead frame 2 Resin 3 Bonding wire 4 Chip 5 Die pad

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　ＩＣの両面面実装においてプリント基
板のプリントパターン配線を簡略化するためにＩＣのリ
ードフレームをＩＣの上部と下部に共通に配置し、ＩＣ
を上向きにも下向きにも実装できる事を特徴としたＩＣ
パッケージ。[Claim 1] In order to simplify the printed pattern wiring of the printed circuit board in double-sided mounting of the IC, the lead frame of the IC is commonly arranged on the upper and lower parts of the IC, and the IC
An IC that can be mounted either upward or downward.
package.
JP3017231A 1991-02-08 1991-02-08 Ic package Pending JPH04256351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3017231A JPH04256351A (en) 1991-02-08 1991-02-08 Ic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3017231A JPH04256351A (en) 1991-02-08 1991-02-08 Ic package

Publications (1)

Publication Number Publication Date
JPH04256351A true JPH04256351A (en) 1992-09-11

Family

ID=11938178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3017231A Pending JPH04256351A (en) 1991-02-08 1991-02-08 Ic package

Country Status (1)

Country Link
JP (1) JPH04256351A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508563A (en) * 1991-03-13 1996-04-16 Kabushiki Kaisha Toshiba Semiconductor assembly having laminated semiconductor devices
US5559365A (en) * 1993-12-28 1996-09-24 Nec Corporation Semiconductor device including a plurality of leads each having two end portions extending downward and upward
DE19650148A1 (en) * 1996-03-27 1997-10-02 Mitsubishi Electric Corp Semiconductor integrated circuit package apparatus
US5760471A (en) * 1994-04-20 1998-06-02 Fujitsu Limited Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plastic package and an outer lead exposed to the outside of a side face of the plastic package
US5801439A (en) * 1994-04-20 1998-09-01 Fujitsu Limited Semiconductor device and semiconductor device unit for a stack arrangement
USRE36077E (en) * 1991-10-15 1999-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing inversion type IC's and IC module using same
US7239008B2 (en) 2001-08-23 2007-07-03 Oki Electric Industry Co., Ltd. Semiconductor apparatus and method for fabricating the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508563A (en) * 1991-03-13 1996-04-16 Kabushiki Kaisha Toshiba Semiconductor assembly having laminated semiconductor devices
USRE36077E (en) * 1991-10-15 1999-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing inversion type IC's and IC module using same
US5559365A (en) * 1993-12-28 1996-09-24 Nec Corporation Semiconductor device including a plurality of leads each having two end portions extending downward and upward
US5760471A (en) * 1994-04-20 1998-06-02 Fujitsu Limited Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plastic package and an outer lead exposed to the outside of a side face of the plastic package
US5801439A (en) * 1994-04-20 1998-09-01 Fujitsu Limited Semiconductor device and semiconductor device unit for a stack arrangement
DE19650148A1 (en) * 1996-03-27 1997-10-02 Mitsubishi Electric Corp Semiconductor integrated circuit package apparatus
DE19650148B4 (en) * 1996-03-27 2005-03-17 Mitsubishi Denki K.K. Semiconductor device and related manufacturing method
US7239008B2 (en) 2001-08-23 2007-07-03 Oki Electric Industry Co., Ltd. Semiconductor apparatus and method for fabricating the same

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