JPH04256355A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a P-channel MOS transistor which does not lower a BVDS even when a channel length is made short by a method wherein an N<+> type layer whose concentration is higher than that of an N-type well layer is formed inside the N-type well layer and a P<+> type source region is formed inside the N<+> type layer. CONSTITUTION:The title device is provided with the following: an N<+> type buried layer 2 formed on a P-type semiconductor substrate 1; an N<-> type epitaxial layer 3 formed on the P-type semiconductor substrate 1; an N-type well layer 4 formed inside the N<-> type epitaxial layer 3; an N<+> type layer 6 which is formed inside the N-type well layer 4 and whose concentration is higher than that of the N-type well layer 4; a P<+> type source region 7 which is formed inside the N<+> type layer 6 and which is formed so as to be shallower than the N<+> type layer 6; and a P<+> type drain region 8 which is formed inside the N-type well layer 4 and which is formed outside the N<+> type layer 6. Thereby, even when a channel length is made short, the hFE of a parasitic lateral PNP transistor does not become large and the breakdown strength between a drain and an N-well is not changed. As a result, it is possible to prevent a drop in a BVDS.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a P-channel MOS transistor having a high drain-source breakdown voltage (hereinafter referred to as BVDS).

0002

2. Description of the Related Art A conventional Bi-CMOS P-channel MOS transistor has a structure as shown in a cross-sectional view of FIG. An N- type epitaxial layer 3 is formed on a P-type semiconductor substrate 1 having an N+-type buried layer 2, and then an N-type well layer 4 is formed from the surface of the N- type epitaxial layer 3.
form. Next, a field oxide film 5 is formed in a region other than the region that will become a transistor, a gate oxide film 9 is grown in the region that will become a transistor, and a gate polysilicon 10 is formed on the gate oxide film 9. Next, P type impurities are ion-implanted to simultaneously form a P+ type source region 7 and a P+ type drain region.

0003

[Problem to be solved by the invention] The above-mentioned P channel M
In an OS transistor, the channel hole current is avalanche multiplied by the large electric field in the drain depletion layer, generating hole-electron pairs, and the electrons flow into the substrate through the N-type well layer and the N+-type buried layer. , a parasitic lateral PNP transistor having a P+ type source region as an emitter, a P+ type drain region as a collector, and an N type well layer as a base operates. Currently, semiconductor devices are becoming highly integrated, and in order to reduce the size of transistors, the channel length is becoming shorter. At this time, P channel MO
The BVDS of the S transistor is not dominated by the drain-N-well breakdown voltage (hereinafter referred to as BVDNwell) and the source-drain punch-through, and is determined by the collector-emitter breakdown voltage (hereinafter referred to as BVCEO) of the parasitic lateral PNP transistor mentioned above. There is a problem of deciding.

At this time, the BVDS of the P-channel MOS transistor is determined by the following equation.

[0005]

[0006] Here, hFE is the current amplification factor of the parasitic lateral PNP transistor. Conventional P-channel MOS
In the case of transistors, when the channel length becomes short, the emitter-collector spacing of the parasitic lateral PNP transistor becomes short, resulting in an increase in hFE and a decrease in BVDS, as is clear from equation (1). was there.

An object of the present invention is to provide a P-channel MOS transistor that does not cause a decrease in BVDS even if the channel length is shortened.

[0008]

[Means for Solving the Problems] A semiconductor device of the present invention includes:
In a P-channel MOS transistor in Bi-CMOS, an N+ type buried layer formed on a P type semiconductor substrate, an N- type epitaxial layer formed on the P type semiconductor substrate, and an N- type buried layer formed within the N- type epitaxial layer. an N-type well layer formed within the N-type well layer and having a higher concentration than the N-type well layer; and a P+-type source formed within the N+-type layer and shallower than the N+-type layer. and a P+ type drain region formed within the N+ type layer and outside the N+ type layer.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 shows a Bi-
FIG. 2 is a structural cross-sectional view of a P-channel MOS transistor in CMOS.

First, the impurity concentration is 1013-1014c.
Arsenic ions are implanted from the surface of the P- type semiconductor substrate 1a of m-3, and the sheet resistance (hereinafter referred to as ρs) is 10-
An N+ type buried layer 2 of 15Ω/□ is formed. after that,
An N- type epitaxial layer 3 with an impurity concentration of 1014-1015 cm-3 is formed, and phosphorus is ion-implanted from the surface of the N- type epitaxial layer 3, so that the impurity concentration is 1015 cm-3.
An N-type well layer 4 of −10 16 cm −3 is formed. Next, phosphorus ions are implanted to form the N+ type collector region 6 of the NPN bipolar transistor.
At this time, an N+ type collector region 6 having an impurity concentration of 1017-1018 cm-3 is formed only on the P+ type source region side, which will be described later. Next, thermal oxidation is performed at 900-1000° C. to form a thick field oxide film 5 of about 1 μm. Next, thermal oxidation is performed at 900-1000° C. to form a gate oxide film 9 with a thickness of 50 nm or less, and a film thickness of about 0.5 μm, ρs =
A gate polysilicon 10 of 20-50 Ω/□ is formed. Next, boron ions are implanted, and the impurity concentration is 1019-10.
A P+ type source region 7 and a P+ type drain region 8 of 20 cm-3 are formed at the same time. At this time, the P+ type source region 7 is formed within the aforementioned N+ type collector region 6.

In the P-channel MOS transistor of this embodiment, since the base concentration of the parasitic lateral PNP transistor is high, both the emitter injection efficiency and the base transport efficiency are reduced, and the hFE of the parasitic lateral PNP transistor is reduced. At this time, B of the P-channel MOS transistor
Since the drain side of the VDNwell has the same structure as the conventional one, the breakdown voltage remains at the conventional level.

FIG. 2 is a structural sectional view of a P-channel MOS transistor in Bi-CMOS for explaining a second embodiment of the present invention.

The P-channel MOS transistor in this embodiment is similar to the first embodiment except that a gate boron region 11 is added which is formed by ion-implanting boron after forming the gate oxide film 9 in the first embodiment. It has the same structure as the example. Therefore, as in the first embodiment, hFE of the parasitic lateral PNP transistor decreases, but B
VDNwell maintains the conventional level. In the case of this embodiment, when forming the gate boron region 11, the impurity concentration of the gate boron region 11 can be controlled by controlling the dose of boron ion implantation. Therefore, the threshold voltage (VT) of the P-channel MOS transistor can be set to be equal to that of a conventional P-channel MOS transistor.

[0014]

[Effects of the Invention] As explained above, the present invention is achieved by forming an N+ type layer with a higher concentration than the N type well layer in the N type well layer and providing a P+ type source region in the N+ type layer. Even if the channel length of the P-channel MOS transistor is shortened, the hFE of the parasitic lateral PNP transistor does not increase, and the drain-N-well breakdown voltage BVDNwell remains the same as before, so even if the channel length is shortened, the BVDS It has the effect of preventing a decline in

[Brief explanation of the drawing]

FIG. 1 is a sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a conventional semiconductor device.

[Explanation of symbols]

1 P-type semiconductor substrate 1a P- type semiconductor substrate 2 N+ type buried layer 3 N- type epitaxial layer 4 N-type well layer 5 Field oxide film 6 N+ type collector area 7 P+ type source region 8 P+ type drain region 9 Gate oxide film 10 Gate polysilicon 11 Gate boron region

Claims (1)

[Claims] [Claim 1] N+ formed on a P-type semiconductor substrate
a type buried layer, and an N- layer formed on the P-type semiconductor substrate.
an N-type epitaxial layer, an N-type well layer formed within the N-type epitaxial layer, an N+-type layer formed within the N-type well layer and having a higher concentration than the N-type well layer, and the N+-type epitaxial layer. a P+ type source region formed within the layer and shallower than the N+ type layer;
A semiconductor device comprising: a P+ type drain region formed within the N+ type layer and outside the N+ type layer.