JPH0425704B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit that eliminates thyristor parasitic effects.

As shown in FIG. 1, a P-type semiconductor substrate 1, an N-type epitaxial layer 2 laminated thereon, and the epitaxial layer 2 are separated into island regions 3 and 4.
A semiconductor comprising a P ⁺ type isolation region 5 , a P ⁺ type diffusion region 6 diffused on the surface of the first island region 3 , and an N ⁺ type diffusion region 7 diffused on the surface of the second island region 4 In the integrated circuit, there is a possibility that a thyristor parasitic effect may occur between the two diffusion regions 6 and 7.

In other words, the P ⁺ -type diffusion region 6 is the emitter or collector region of a lateral transistor or a P-type diffused resistor biased to a high potential, and the N ⁺ -type diffusion region 7 is a tunnel resistor or epitaxial resistor biased to a low potential. In the case of a terminal, a PNPN self-biased parasitic thyristor is formed by the P ⁺ type diffusion region 6, the N type first island region 3, the P ⁺ type isolation region 5, and the N type second island region. Then, the parasitic thyristor turns on and a parasitic current flows as shown by the arrow.

Figure 2 is an equivalent circuit diagram of a parasitic thyristor.
Tr ₁ is a PNP transistor formed of a P ⁺ type diffusion region 6 N type first island region 3 and a P ⁺ type isolation region 5, and Tr ₂ is an N type first island region 3 P ⁺ type isolation region. This is an NPN transistor formed of a region 5 and an N-type second island region 4.

Such a parasitic thyristor effect occurs when the power supply terminal is inserted into the socket before the ground terminal that is in contact with the semiconductor substrate 1, and the substrate potential rises, resulting in a voltage drop of several 100 mA even if the ground terminal is inserted into the socket.
current continues to flow.

The present invention has been made in view of these drawbacks and provides a semiconductor integrated circuit that prevents the conventional thyristor parasitic effects. Embodiments of the present invention will be described in detail below with reference to FIGS. 3 and 4.

As shown in the third section, the semiconductor integrated circuit according to the present invention includes a P-type semiconductor substrate 11, an N-type epitaxial layer 12 laminated thereon, and a P-type semiconductor substrate 11, an N-type epitaxial layer 12 laminated thereon, and a P-type semiconductor substrate 11 in which the epitaxial layer 12 is formed in each island region 13, 14. Separate P ⁺
A type separation region 15, a P ⁺ type diffusion region 16 provided on the surface of the first island region 13, an N ⁺ type diffusion region 17 provided on the surface of the second island region 14, and a shot that is a feature of the present invention. It is composed of key barrier diodes 18, 18.

A Schottky barrier diode 18 is formed on the surfaces of the first and second island regions 13 and 14. That is, the oxide film 19 on the surfaces of the first and second island regions 13 and 14 is selectively removed and an aluminum layer is deposited. The shot key barrier diode 18 of the first island region 13 is connected in the forward direction between the P ⁺ type diffusion region 16 and the first island region 13, and the shot key barrier diode 18 of the second island region 14 is connected in the forward direction between the P + type diffusion region 16 and the first island region 13. are adjacent first and second island regions 13,
The isolation region 15 between the islands 14 and the second island region 14 are connected in the forward direction. Such a connection means may be made of vapor-deposited aluminum as shown in FIG.

An equivalent circuit diagram of the structure of the present invention is shown in FIG. That is, Tr ₁ is a PNP transistor formed of a P ⁺ type diffusion region 16, an N type first island region 13, and a P ⁺ type isolation region 15, and Tr ₂ is a PNP transistor formed of an N type first island region 13P ⁺ type. is an NPN transistor formed by an isolation region 15 and an N-type second island region 14, _SD1 is a Schottky barrier diode formed in the first island region 13,
SD ₂ is a Schottky barrier diode formed in the second island region 14. In this circuit, the base-emitter of Tr ₁ is forward biased by SD ₁ and held at approximately 0.3V, so Tr ₁ is not turned on.
Furthermore, since the voltage between the base and emitter of Tr ₂ is similarly maintained at approximately 0.3V by SD ₂ , Tr ₂ is not turned on either.

As detailed above, in the present invention, shot key barrier diodes SD ₁ and SD ₂ are formed in the first and second island regions 13 and 14, and the parasitic transistors are
Simply biasing the base emitters of Tr ₁ and Tr ₂ to about 0.3V is beneficial in completely preventing parasitic thyristor effects. Furthermore, the present invention has the advantage that it can be realized without adding any new manufacturing steps.

[Brief explanation of drawings]

FIG. 1 is a sectional view for explaining a conventional example, FIG. 2 is an equivalent circuit diagram for the conventional example, FIG. 3 is a sectional view for explaining the present invention, and FIG. 4 is an equivalent circuit diagram for the present invention. Explanation of main drawing numbers, 11...P-type semiconductor substrate,
12... N-type epitaxial layer, 13, 14...
... first and second island regions, 15 ... P ⁺ type isolation region, 16 ... P ⁺ type diffusion region, 18 ... Schottky barrier diode.

Claims (1)

[Claims] 1 comprising a semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type provided on the substrate, and a separation region of one conductivity type that separates the epitaxial layer into a plurality of island regions, a first island region; In a semiconductor integrated circuit in which a thyristor parasitic effect occurs between a diffusion region of one conductivity type on the surface and a diffusion region of the opposite conductivity type on the surface of an adjacent second island region, 1. A semiconductor integrated circuit comprising a Schottky barrier diode, the diode being connected between the diffusion region of one conductivity type and the first island region and between the isolation region and the second island region.