JPH0425709B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit device. More particularly, the present invention relates to device structures for improving the DC gain and figure of merit of integrated injection logic devices.

[Prior art]

Integrated Injection Logic Element
Logic (hereinafter abbreviated as I ² L element) is widely used as a bipolar highly integrated logic element.
However, the I ² L element uses a vertical inverted NPN transistor, and has the drawback that its effective current gain (β _ieff ) is inherently small. For this I ² L
When manufacturing bipolar ICs including elements,
In order to control this current gain to a value higher than a necessary value, there are problems such as a relatively small margin for manufacturing process conditions.

[Purpose of the invention]

An object of the present invention is to provide an I ² L element structure with a large effective current gain (β _ieff ) and a good figure of merit.

[Summary of the invention]

FIG. 1 is a circuit diagram illustrating the effective current gain (β _ieff ) of the I ² L element. The minimum required β _ieff conditions for the I ² L circuit to operate logically are as follows.

β _ieff = I _C /I _B , I _B = I _BO + I _R I ² Operating conditions of the L circuit: β _ieff > 1 Note that I _C , I _B , I _BO and I _R are the currents shown in Figure 1. .

The effective current gain (β _ieff ) of an I ² L element is the base current I _B and collector current when the injector is grounded.
The ratio of I _C , I _B, is the sum of the injector return current I _R in addition to the base current I _BO of the inverse NPNT ^r Q ₂ .
This _IR is originally unnecessary for operation. According to the inventor's measurements, in the conventional structure I ² L, I _R is I _BO
, which makes β _ieff unnecessarily small. As an example of actual measurement value, I _R = 1.5l _BO
It was hot. Therefore, ideally when I _R = 0, β _ieff
= I _C /I _BO , whereas I _R = 1.5I _BO , so β _ieff = I _C /I _BO + I _R = 0.4×I _C /I _BO .

In this way, it was found that the reduction was 0.4 times compared to the ideal case.

Therefore, it has been found that reducing the injector return current I _R is extremely important in order to improve the effective current gain of the I ² L element. Based on the above results, the present invention provides a structure that reduces _IR by providing an obstacle for holes in the opposing portions of the emitter and collector of an injector PNP transistor.

That is, the representative invention disclosed in this application is
A plurality of integrated injection logic elements each comprising a horizontal injector PNP transistor and a vertical reverse PNP transistor sharing the P-type collector region 42 of the injector PNP transistor as its P-type base region; A collar region 52 is formed on the surface of the semiconductor substrate around the shared P-type region 42 of the logic element.
each P-type emitter region of the injector PNP transistor of the plurality of integrated injection logic elements is P
A type injector region 41 is formed on the surface of the semiconductor substrate, and the shared P-type region of each of the plurality of integrated injection logic elements is formed on the surface of the semiconductor substrate in a direction substantially parallel to the length direction of the P-type injector region. In a semiconductor integrated circuit device in which the collar regions are formed on the surface of the semiconductor substrate so as to sandwich the same, a separation distance substantially parallel to the length direction of the collar regions formed with the shared P-type region sandwiched therebetween.
(B), means 501 for reducing the effective emitter-collector opposing length (B) of each emitter-collector opposing portion of the injector PNP transistor, which is substantially parallel to the length direction, of the plurality of integrated injection logics. The device is characterized in that it is provided at each emitter-collector facing portion of the injector PNP transistor of the device.

[Embodiments of the invention]

FIGS. 2a and 2b are a plan view and a cross-sectional view, respectively, showing the first embodiment of the present invention. In this embodiment, the same shallow N ⁺ that constitutes the collar 52 of the I ² L element
A hole obstruction 501 is formed by a diffusion layer, and the injector facing length [A] is made narrower than the conventional value [B]. By configuring all gates of the required I ² L circuit with this structural element, in principle, the injector return current was reduced and β _ieff was improved.

Here, the manufacturing method of the first embodiment will be described with reference to FIG. This structure is obtained by the well-known bibolar IC manufacturing process as follows. Each step is a well-known method and the main points will be briefly described. First, a high concentration n-type impurity is diffused into a desired location on a P ^- substrate 1 made of silicon or the like to form an n ⁺ buried layer 2 . Next, the n-type layer 3 is grown by 0.5 to 20 μm using a well-known epitaxial growth method doped with impurities such as phosphorus.
About m is deposited. Thereafter, p-type impurities such as boron are diffused into desired locations on the surface, and the p-type layers 41, 4 are
form 2. Next, n-type impurities such as phosphorus and arsenic are diffused to desired locations on the surface, and the n ⁺ layer 51,
52,501 is formed. Next, a contact hole is opened at a desired location in the SiO ₂ layer 7 on the surface, and Al is deposited thereon by vapor deposition or the like. Thereafter, a pattern is formed by photoetching to form Al electrodes 8 for leading out each terminal. Through the above procedure, the structure shown in FIG. 2 is obtained. Of course, if necessary, in addition to the structure shown in FIG. 2, a PSG film or the like for surface protection may be applied over the entire surface. Alternatively, an organic resin (for example, polyimide resin, etc.) or other insulating film may be used as an interlayer insulating film to form two-layer wiring of Al. It goes without saying that the present invention is equally effective in these cases as well.

FIGS. 3 to 6 are diagrams illustrating a second embodiment of the present invention. First, FIG. 3 shows a plan view of four implemented I ² L element structures.

In the figure, numeral 41 indicates a planar region of the P-type layer which becomes the injector of the I ² L element. Similarly 42
51 indicates the P-type layer which becomes the base of the inverted NPN transistor of the I ² L element, 51 indicates the N ⁺ layer which becomes the collector of the inverted NPN transistor of the I ² L element, and 52 indicates the N ⁺ layer which becomes the collar of the I ² L element. ing. A, as in FIG. 2, shows the narrowed opposing length of the injector. B indicates the width of the P-type region that becomes the base of the inverse NPN transistor of the I ² L element. A has a conventional structure (100% aperture ratio), b and c have an aperture ratio of 63% and
30% structure, d is 100% closed structure (opening ratio 0%)
It is. Here, the aperture ratio of the injector opposing length is defined by A/B in the figure. Although d has an aperture ratio of 0%, in this example, a shallow N ⁺ diffusion layer forms an obstacle, so holes pass under it, and the structure d also operates. In the present invention, 0%<opening ratio<100%
This is based on the discovery that this structure has a significant effect. FIG. 4 shows the relationship between the effective current gain β _ieff and the aperture ratio of the I ² L element. Assuming that the conventional structure (100% aperture ratio) is 1, β _ieff is gradually improved as the aperture ratio is reduced to 0%. Therefore, an arbitrary value of the aperture ratio between 0% and 100% has the effect of improving β _ieff . On the other hand, as the aperture ratio decreases,
Data was obtained that showed a decrease in the operating speed of the I ² L device.
Figure 5 shows an I ² L ring oscillator (1 collector type I ² L
Minimum delay time of each structure evaluated using
t _pdnio is shown. When the aperture ratio is decreased from 100% to 0%, the delay time also increases monotonically and the operation speed decreases. As a logic element, it is desirable that the delay time is also small. Therefore, we now consider F=β _ieff /t _pdnio as the figure of merit F of the I ² L element, and consider that the larger F is, the better. FIG. 6 is a plot of this F and the aperture ratio. From the figure, it can be seen that the effect of F clearly increases when the aperture ratio is about 16% to 85%, and it becomes substantially maximum when the aperture ratio is about 30% to 70%, and the effect is large.

When constructing an integrated circuit having I ² L elements, the entire circuit is laid out as shown in FIG. 2 using I ² L elements having a predetermined aperture ratio value as described above. Here, in principle, it is important to make the aperture ratios equal within one circuit block as in the example shown in FIG. Therefore, the present invention is based on the principle that at least one circuit block is constructed of I ² L elements having a certain aperture ratio A/B.

It should be noted that there are some reported examples of device structures such as those shown in FIGS. 3b and 3c.

See, for example, US Pat. No. 3,989,957 and others. However, in these examples, by reducing the facing length and slowing down only the specifically desired gates in the circuit block, special functions such as matching gate delay times and configuring multivalued logic circuits can be achieved. This is what we do. Therefore, the purpose and structure of the present invention are different from that of the present invention, in which the opposing lengths of all gates in a circuit block are reduced in principle in order to improve the effective current gain.

In addition, in principle, all gates (I ² L elements)
I will provide a supplementary explanation of the meaning. First, even in the I ² L circuit of this structure, the speed can be changed by changing the aperture ratio of only some desired gates. For example, if only a desired gate has a conventional structure, the speed of only that gate can be increased. Second, the effective current gain of the I ² L element is I ² L
It is a fact that the larger the number of collectors (fanout number) of an element, the smaller it is generally. Therefore, circuit blocks that require high speed on the chip of an integrated circuit device are designed with an aperture ratio of 100% while maintaining high speed.
Gain can be secured by designing a circuit with a relatively small fan-out number, and other circuit blocks can be constructed using the present structural element so that the fan-out number can be increased. "In principle, all gates of at least one circuit block"
This meaning includes cases such as those mentioned above.

FIG. 7 is a cross-sectional structural diagram showing a third embodiment of the present invention. In this embodiment, the N ⁺ color 501 is configured to be in contact with (or partially overlap with) the injector, thereby effectively imparting a concentration gradient from the injector to the base region. This results in
The reduction in injector current gain due to the insertion of the N ⁺ collar is reduced, and the effective current gain can be improved while minimizing the increase in power consumption.

FIG. 8 is a cross-sectional structural diagram showing a fourth embodiment of the present invention. A similar structure is realized by the collar of the deep N ⁺ diffusion layer 501, and a similar effect is obtained.

FIG. 9 is a cross-sectional structural diagram showing a fifth embodiment of the present invention. In this embodiment, a groove 601 formed on the surface by Si etching or other method is used to form a collar and hole obstruction of the I ² L element, thereby obtaining a similar structure and effect.

FIG. 10 is a cross-sectional structural diagram showing a sixth embodiment of the present invention. In this example, insulators (71 and 70
1) There is a method that forms an obstacle between the collar and the hole to obtain a similar effect. In this example, as an insulator
Although SiO ₂ was used, other materials such as Si ₃ N ₄ may also be used.

FIG. 11 is a cross-sectional structural diagram showing a seventh embodiment of the present invention. In this example, the present structure is applied to an I ² L element having a phosphorus-embedded structure, and similar effects are obtained. In Fig. 11, 1 is a P ^-silicon substrate,
21 is the first N ⁺ buried layer (an N ⁺ layer using impurities with a small diffusion coefficient such as antimony or arsenic), and 22 is the second N ⁺ buried layer (using impurities with a large diffusion coefficient such as phosphorus). (N ⁺ layer). A shaped layer 3 is formed on such an N ⁺ buried layer, and I ² L elements and the like are formed within this N-type layer 3. 2nd with the code in Figure 11
Items that are the same as those in the figure indicate the same parts.

501 is the N ⁺ layer which becomes the color according to the present invention.

FIG. 12 is a cross-sectional view of a conventional I ² L element having a phosphorus-embedded structure. The area of 1000 is
The region 2000 in the PNP transistor section indicates the I ² L element. In FIG. 12, the same parts as in FIGS. 2 and 11 are indicated by the same reference numerals.

Note that FIG. 11 shows only the I ² L element part.
If a configuration is adopted in which the NPN transistor section and the I ² L element coexist, the I ² L section and the section 1000 in FIG. 12 will coexist.

When an I ² L circuit and a bipolar transistor circuit (NPNTr, etc.) are integrated on the same chip,
In NPN transistors, N ^- layer 3 is used to improve breakdown voltage.
In the I ² L circuit, we want to increase the thickness of the N ^- layer 3 to improve the gain. Therefore, this is achieved by providing the phosphorus buried layer 22 with a large thermal diffusion coefficient in the I ² L circuit. FIG. 13 is a schematic diagram of the impurity profile of a typical phosphorus-embedded structure I ² L device. Here, looking at the total concentration profile (thick solid line) of the N ⁺ buried layer, the concentration shows a steep change and decreases as it approaches the surface, and the concentration of the N ^- layer becomes dominant near the surface. . That is, although the concentration immediately below the base of the I ² L element is sufficiently increased, the base portion of the PNPTr, which serves as an injector, remains at a low concentration because it is near the surface. Therefore, in the element with the conventional structure, the injector return current is not reduced. When the technical concept of the present invention is applied to an I ² L element using a phosphorus buried layer, a large effective current gain improvement effect can be obtained together with the βi improvement effect due to the phosphorus buried layer.

〔Effect of the invention〕

As described above, the present invention has the effect of improving the effective current gain β _ieff by reducing the injector return current of the I ² L element. Also, the result is the reverse NPNTr
Even if the gain βi of the main body is smaller than that of the conventional structure, normal operation can be ensured in the I ² L circuit. In addition, it is possible to widen the permissible fluctuation range of manufacturing process conditions when manufacturing an I ² L element, resulting in the effect that I ² L LSI is easier to manufacture.

In the present invention, the same effect can be obtained even if the polarities of all P-type and N-type in each region such as the semiconductor layer are reversed.

[Brief explanation of drawings]

FIG. 1 is a theoretical connection diagram for explaining the effective current gain of an I ² L element, FIGS. 3 is a planar structural diagram showing the second embodiment of the present invention, FIG. 4 is a diagram showing the relationship between the aperture ratio and effective current gain, FIG. 5 is a diagram showing the relationship between the aperture ratio and minimum delay time, and FIG. Fig. 6 is a diagram showing the relationship between the aperture ratio and the F factor, Figs. 7 to 11 are cross-sectional views of a device showing an embodiment of the present invention, and Fig. 12 has a phosphorus-embedded structure.
FIG. 13 is a cross-sectional structure diagram showing a conventional structure of an I ² L element, and a diagram showing an impurity profile of an I ² L element having a phosphorus buried structure. 1...P ^- (silicon) substrate, 2...N ⁺ buried layer,
21...First N ⁺ buried layer (impurity with a small diffusion coefficient such as antimony or arsenic), 22...Second N ⁺
Buried layer (impurities with large diffusion coefficients such as phosphorus), 3
...N-type layer, 31 ...P ⁺ separation region, 41 ...I ² L
P-type layer serving as an injector of the element, 42...I ² L
P-type layer serving as the base of the inverse NPN transistor of the element, 43...P-type layer serving as the base of the NPN transistor, 51...N ⁺ layer serving as the collector of the inverse NPN transistor of the I ² L element, 52...I ² N ⁺ layer which becomes the collar of L, 53...N ⁺ layer which becomes the emitter of the NPN transistor, 501...N ⁺ layer which becomes the hole obstruction of the injector of ^I2L , 61...becomes the collar of ^I2L Groove, 601... Groove that becomes an obstruction to the injector hole of I ² L, 7... SiO ₂ layer, 71... I ² L
701...SiO ₂ layer which becomes the hole obstruction of the injector of I ² L, 8... _Al
Electrode, 1000...NPN transistor, 200
... ^I2L element.

Claims (1)

[Claims] 1. A plurality of integrated injection logic elements comprising a horizontal injector PNP transistor and a vertical reverse NPN transistor that shares the P-type collector region of the injector PNP transistor as its P-type base region. , a collar region is provided on the surface of the semiconductor substrate around the shared P-type region of the plurality of integrated injection logic elements, and each P-type emitter region of the injector PNP transistor of the plurality of integrated injection logic elements has a P-type emitter region.
forming the shared P-type region of each of the plurality of integrated injection logic elements in a direction substantially parallel to the length direction of the P-type injector region on the surface of the semiconductor substrate; In a semiconductor integrated circuit device in which the collar region is formed on the surface of the semiconductor substrate so as to sandwich the common P-type region, a separation distance substantially parallel to the length direction of the collar region formed with the shared P-type region sandwiched therebetween. A means for reducing an effective emitter-collector opposing length substantially parallel to the length direction in the emitter-collector opposing portion of the injector PNP transistor of the plurality of integrated injection logic elements is provided. A semiconductor integrated circuit device comprising the above-mentioned emitter-collector opposing portions. 2. In each of the emitter-collector opposing portions of the injector PNP transistors of the plurality of integrated injection logic elements, the effective emitter-collector opposing length is set to 16% to 85% of the separation distance. Claim 1
The semiconductor integrated circuit device described in . 3. In each emitter-collector opposing portion of the injector PNP transistor of the plurality of integrated injection logic elements, the effective emitter-collector opposing length is set to 30% to 70% of the separation distance. Claim 1
The semiconductor integrated circuit device described in . 4. Claims 1 and 2, characterized in that the above means is formed by using at least one means selected from the group consisting of a groove, an insulator region, an N-type region, and a highly doped N-type region. Or the semiconductor integrated circuit device according to item 3. 5. The means is provided to extend from the collar region to the surface of the semiconductor substrate between the P-type injector region and each of the shared P-type regions of the plurality of integrated injection logic elements. A semiconductor integrated circuit device according to claim 1, 2, 3, or 4.