JPH04257154A - Speech path data test system - Google Patents

Abstract

PURPOSE:To surely detect trouble by extracting only check data of an idle channel to output and feed back it to a line controller and comparing this feedback data with output check data preliminarily outputted from the line controller itself. CONSTITUTION:A higher-order main switch device 3 which concentrates and multiplexes speech paths from plural subscriber controllers 1 and a line controller 4 which controls this switch device 3 are provided. The controller 4 writes check data in an idle channel 26 of audio data from a switch device 2 and outputs it to the line multiplexing switch 3. The switch 3 extracts only check data of the idle channel 26 from this audio data and outputs and feeds back it to the controller 4. The controller 4 compares this feedback data with output check data preliminarily outputted from the device 4 itself, thereby surely detecting trouble of speech path data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication path data testing method for detecting failures in communication paths between a main switching device and a line concentrator multiplexing device in an electronic switching system.

0002

2. Description of the Related Art FIG. 2 shows the overall configuration of this type of electronic exchange system. In electronic switching processing, subscriber telephone 1
3 through the subscriber control unit (SLC) 1 is condensed, that is, multiplexed, by the concentrator and multiplexer (LC) 14, and sent to the main switching device (DSM) 2, where the voice data is A process is performed in which data is time-divided, switched to an arbitrary time slot, and sent out.

The main switching device (DSM) 2 is controlled by a main controller (CPR) 15, and the line concentrator (LC) 14 is controlled by a line controller (LPR) 4. And the line control device (LPR) 4
is controlled by a main controller (CPR) 15 through inter-processor communication through a high speed communication path (HW) 16.

[0004] Focusing only on the voice data route, the data communication route is connected to the main switch device (
DSM) 2 to the network interface (NWIF) 17 in the line concentrator (LC) 14 and the line multiplex switch (LTSW) via the high speed communication path (HW) 16.
3 to subscriber controller (SLC) 1 → subscriber telephone 13
It is connected to the. Then, the main switch device (DS
Between M) 2 and the line multiplexing switch (LTSW) 3, there is a pair of identical devices, that is, a duplex structure. Some of the duplex communication paths are intertwined, and for example, the network interface (NWIF) 1
7 is switched.

[0005] In such a duplex structure, one system is normally used as the active system, and if a failure occurs in this one system, the other backup system switches to the active system.
Processing will continue.

[0006]

[Problem to be Solved by the Invention] As described above, telephone switching systems have a duplex system structure in case a failure occurs or for maintenance purposes, but there is no data failure detection means. I wasn't prepared.

[0007] Therefore, when a failure occurs in the system, an operator inspects the system based on an inquiry from a subscriber, and takes actions such as disconnecting the faulty processing system from the active system. .

The present invention has been made in view of the above-mentioned problems, and its purpose is to improve communication paths, particularly line control equipment (LPR).
An object of the present invention is to provide a technology that can reliably detect a data failure in a communication path between a line multiplexing switch (LTSW) 3 and a line multiplexing switch (LTSW) 3.

[0009]

[Means for Solving the Problems] The present invention provides a line multiplexing switch that concentrates and multiplexes communication paths from a plurality of subscriber control units (SLCs) 1 and connects them to an upper main switching device (DSM) 2. (LTSW) 3 and this line multiplexing switch (
In a telephone switching system comprising a line control device (LPR) 4 that controls a line control device (LTSW) 3, the line control device (LP
R) 4 writes check data into an empty channel (26) in the audio data from the main switching device (DSM) 2 and outputs it to the line multiplexing switch (LTSW) 3, and performs the line multiplexing. The switch (LTSW) 3 extracts only the check data of the vacant channel (26) from this audio data and outputs the check data back to the line control device (LPR) 4.
The gist of PR) 4 is to compare this feedback data with the output check data previously output by itself to detect a failure in the communication path data.

0010

[Operation] FIG. 1 shows the above-mentioned means in a principle diagram.

That is, the main switch device (DSM)
2 and a line concentrator (LC) 14 including a line multiplexing switch (LTSW) 3 are connected by a high speed communication path (HW) 16, and communication is performed in periodic units of time slots of about 128 channels. ing.

By the way, the main switch device (DSM)
2 and the line concentrator (LC) 14 (
Not all of the data in the HW) 16 stores audio data, but some of the data is for inter-processor communication between the main controller (CPR) 15 and the line controller (LPR) 4. It also includes control data, etc. These control data are necessary only between the main switch device (DSM) 2 and the network interface (NWIF) 17, and are necessary only between the main switch device (DSM) 2 and the network interface (NWIF) 17, and the line control device (LPR) 4
The storage channel for this control data is an empty channel between the line concentrator and multiplexer (LC) 14.

Therefore, the present inventor focused on the occurrence of this empty channel, and wrote check data into this empty channel to connect the line controller (LPR) 4 and the line concentrator/multiplexer (LPR).
C) It was decided to detect failures in the communication path data between the two parties.

That is, in the line control device (LPR) 4,
When an empty channel is detected in the audio data from the upper main switching device (DSM) 2, check data is written to this empty channel, and the line multiplexing switch (LTSW)
)3. Upon receiving this, the line multiplexing switch (LTSW) 3 extracts only the check data from the vacant channels, and distributes and outputs the remaining audio data channels to the subscriber control unit (SLC) 1, respectively. The extracted check data is the line control equipment (LPR)
4 is fed back and output. The line controller (LPR) 4 compares the returned check data with the previous check data, and if the two do not match, the line controller (LPR) 4 stores the memory in the line multiplexing switch (LTSW) 3 or the communication path. detected as a failure.

[0015]

Embodiment FIG. 4 shows an embodiment of the present invention. The overall configuration of the system in this example is shown in Figure 2 described earlier.
Since it is the same as that in FIG. 3, the explanation will be omitted.

The line controller (LPR) 4 controls the line concentrator and multiplexer (LC) 14, and mainly monitors line concentration instructions, hooking ON/OFF, dial pulse counts, and the like. A line multiplexing switch (LTSW) 3 that constitutes a part of a line concentrator (LC) 14 has a downstream communication memory (DSPM) 10 and an upstream communication memory (USPM) 12.
It is equipped with two types of memories that function as time switches for the downlink communication path 8 and uplink communication path 11, respectively, and the distribution of time division multiplexed data on the downlink communication path 8 and the uplink communication path 11, and the distribution of time division multiplexed data on the downlink communication path 8 and the uplink communication path 11, and the parallel input from the subscriber control unit (SLC) 1. The incoming data is multiplexed.

The line control device (LPR) 4 includes a microprocessor (
MPU) 18, this microprocessor (
The line control memory (LC) is connected to the line control memory (LC) via the bus 20.
M) 9 is connected. This line control memory (LCM)
9 is a downstream communication memory (DSPM) 10 and an upstream communication memory (USPM) in the line multiplexing switch (LTSW) 3.
PM) 12 to output a control signal.

[0018] Normal audio data transmission can be realized only with the above configuration. That is, microprocessor (MPU
) 18 writes the number of the time slot to be output to a predetermined address of the line control memory (LCM) 9 via the bus 20. Based on this, line control memory (LCM)
9 instructs the downlink memory (DSPM) 10 and the uplink memory (USPM) 12 to read/write to realize switching. As a result, time-sharing data is delivered to the desired subscriber control unit (SLC) 1. Data from the subscriber control unit (SLC) 1 is also multiplexed in the same manner and sent to the main switch unit (DSM).
)2.

In this embodiment, in addition to the above-described configuration, the following devices are added to enable failure detection of communication path data.

In the line control device (LPR) 4, the line multiplexing switch (LTS) is connected from the main switch device (DSM) 2 to the line control device (LPR) 4.
W) A first selector (SEL-
1) 21 is provided, and this first selector (SEL
-1) Check data from the check data generation circuit 5 constituted by RAM or ROM is inputted to 21 along with data from the main switch device (DSM) 2. Further, the first selector (SEL-1) 21 is instructed by the timing circuit (TMG) 6 to switch the input system. Furthermore, the bus 2 in the line control device (LPR) 4
A comparison circuit (MAT) 7 is connected to the terminal 0, which compares the data from the check data generation circuit 5 with data from the line multiplexing switch (LTSW) 3, which will be described later, and sends the result onto the bus 20. The fault register (R
EG) Write in 23.

A second selector (SEL-2) 24 is provided on the uplink communication path 11 in the line multiplexing switch (LTSW) 3, and the input from the subscriber controller (SLC) 1 and the downlink communication memory ( The return input from the DSPM) 10 is switched and written into the uplink communication memory (USPM) 12.

In the line control device (LPR) 4, the line multiplexing switch (LTSW) 3 is connected to the main switch device (
The data receiving circuit 2 is connected to the upstream communication path 11 leading to the DSM) 2.
5 is provided, and the uplink call memory (USPM)
It is possible to read only a predetermined channel from the data from 12 and output it to a comparison circuit (MAT) 7.

Next, a procedure for detecting a data failure in the above device configuration will be explained. First, the main switch device (D
One cycle of data transmitted between SM) 2 and line concentrator (LC) 14 is 12 as shown in Figure 5(a).
It is composed of 8 channels, of which 120 channels store audio data, and 6 channels store auxiliary data such as BUSY tones. The remaining two channels normally store control data for inter-processor communication between the main controller (CPR) 15 and the line controller (LPR) 4. Therefore, the high speed communication path (H
W) 16, there are no empty channels in the data, but at the stage when this data is transmitted from the main switching device (DSM) 2 to the line concentrator (LC) 14,
Since the previous control data is no longer needed, two channels become free space.

In this embodiment, attention is paid to the occurrence of this empty channel 26 in the line control device (LPR) 4, and the timing circuit (TMG) 6 generates a signal as shown in FIG. 5(b) in response to this empty channel 26. A timing signal is sent out, and the input of the first selector (SEL-1) 21 is switched to the input from the check data generation circuit 5 for one channel. This allows the check data to be written into the empty channel 26 without affecting other audio data channels at all.

[0025] Then, the data passes through the downlink communication path 8 and is transferred to the downlink communication memory (in the line multiplexing switch (LTSW) 3).
DSPM) 10. At this time, the microprocessor (MPU) 18 in the line control device (LPR) 4 transmits the downlink call memory (D) to the line control memory (LCM) 9.
By instructing to sequentially write the check data to all addresses of SPM) 10, it becomes possible to check all addresses by writing data a predetermined number of times.

The check data written in the downlink communication memory (DSPM) 10 is read out sequentially together with other voice data, but the
The timing circuit (TMG) 6 of R) 4 outputs the second selector (SEL) in synchronization with the reading of this check data.
-2) 24 is controlled, the read check data is written to the free channel 26 of the voice data from the subscriber controller (SLC) 1, and this data is in turn stored in the uplink memory (USPM) 12. will be written to. At this time, this check data can be sequentially written to all addresses of the uplink communication memory (USPM) 12 according to instructions from the line control memory (LCM) 9, as described above.

The data written in the uplink communication memory (USPM) 12 is sequentially read out and transmitted through the uplink communication path 11 to the line control device (LPR) 4 and the main switch device (D
SM) Output in two directions.

Next, as shown in FIG. 7, the data receiving circuit 25 reads only the channel portion in which the check data is stored from the data from the upstream communication memory (USPM) 12, and sends this to the timing circuit ( TMG)6
The signal is outputted to the comparator circuit (MAT) 7 at the timing given by .

The comparison circuit (MAT) 7 compares the check data from the check data generation circuit 5, which is synchronously inputted by the timing circuit (TMG) 6, and the feedback data written to a predetermined channel of the upstream communication path 11. If there is a difference between the two, register the fault register (REG).
23 is rewritten to "1". The microprocessor (MPU) 18 always registers this fault register (REG).
) 23, and a data failure can be detected by a change in the bit state of the failure register (REG) 23.

That is, when a discrepancy between data is detected in the comparison circuit (MAT) 7, the downlink communication memory (DSPM) 10 or the uplink communication memory (USP
M) This is a case where there is a mismatch between the written data and the read data of 12, which means that a failure has occurred in the data on the communication path.

As described above, according to this embodiment, from the line control device (LPR) 4 to the line multiplexing switch (LTSW) 3
Focusing on the fact that an empty channel 26 occurs in the voice data on the communication path leading to the communication path, by storing check data in this empty channel 26, the communication path can be completed without affecting the normal voice data transmission. Data testing becomes possible.

[0032] In the above embodiment, an example was explained in which the communication path data test was performed using the active system while continuing normal voice data exchange processing, but the communication path data test was performed in the backup system. In some cases, the high speed communication path (HW) 16 between the main control unit (CPR) and the line control unit (LPR) is
Also, since an empty channel can be secured in the audio data, it is possible to write/read check data to/from the main switch (DSM) 2 by writing the check data to this empty channel. Therefore, it is also possible to detect failure processing in the main switch (DSM) 2 for the standby system.

[0033]

According to the present invention, it is possible to reliably and easily detect the occurrence of a data failure in a communication path, particularly in a communication path between a line control device and a line multiplexing switch.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the principle of the present invention.

FIG. 2 is a block diagram showing the overall configuration of an electronic exchange system in the prior art and the present invention.

FIG. 3 is a block diagram showing the configuration of a line concentrator multiplexing device in the prior art and the present invention.

FIG. 4 is a block diagram showing a line control device (LPR) and a line multiplexing switch (LTSW) in an embodiment.

FIG. 5(a) is an explanatory diagram showing the data structure in the example, and FIG. 5(b) is a timing chart showing its import timing.

FIG. 6 is a flow diagram showing data failure detection processing in the embodiment.

FIG. 7 is a functional block diagram showing failure detection processing in the embodiment using data paths between devices.

[Explanation of symbols]

1 Subscriber control device (SLC) 2 Main switch device (DSM) 3 Line multiplexing switch (LTSW) 4 Line control device (LPR) 5 Check data generation circuit 6 Timing circuit (TMG) 7 Comparison circuit (MAT) 8 Downlink Communication path 9 Line control memory (LCM) 10 Downlink communication memory 11 Uplink communication path 12 Uplink communication memory 13 Subscriber telephone 14 Line concentrator (LC) 15 Main controller (CPR) 16 High speed communication path (HW) 17 Network interface (NWIF)1
8 Microprocessor (MPU) 20 Bus 21 First selector (SEL-1) 23 Fault register (REG) 24 Second selector (SEL-2) 25 Data receiving circuit 26 Empty channel

Claims (3)

[Claims] 1. A line multiplexing switch (3) that concentrates and multiplexes communication paths from a plurality of subscriber control devices (1) and connects it to an upper main switch device (2); 3), and the line control device (4) controls the main switch device (2).
Check data is written into the empty channel (26) in the audio data from the audio data and output to the line multiplexing switch (3), and the line multiplexing switch (3) writes the checking data into the empty channel (26) from the audio data. 26) is extracted and output as feedback to the line control device (4), and the line control device (4) compares this feedback data with the output check data previously output by itself. A communication path data testing method characterized by detecting failures in communication path data. 2. In claim 1, the line control device (4)
It includes a check data generation circuit (5) that generates check data, a timing circuit (6) that detects an empty channel in the audio data and provides timing for writing data to the empty channel, and a timing circuit (6) that generates check data. The comparator circuit (7) is provided with a comparator circuit (7) that inputs check data and feedback data from the data generation circuit (5) in synchronization with the timing circuit 6.
A communication path data test method is characterized in that a data failure signal is output only when the check data and feedback data do not match. [Claim 3] In claim 1, the line multiplexing switch (3) includes a downlink memory (10) provided on the downlink path (8) and a downlink memory (10) provided on the uplink path (11). The check data written by the check data generation circuit 5 is provided with an uplink call memory (12) and an uplink call memory (10).
2) are sequentially written and read to the line control device (
4) A communication path data test method characterized in that feedback output is performed.