JPH0425778A - Parallel interface - Google Patents

Abstract

PURPOSE:To contrive a reduction of the number of signal transmission lines independent of the number of measuring parts by making plural data latch circuits to operate in the manner of time-dividing them to plural time slots and transferring plural groups of parallel data by a common data latch circuit. CONSTITUTION:The plural data latch circuits 10A-10D, 13A-13D transferring the parallel data such as plural test requiring signals RQ1-RQ4 and RQ5-RQ8, etc., are made to operate with time-dividing them respectively, and the parallel data are discriminated by required block select signals BC11, BC12, BC21, BC22, etc. Thus, the scale of circuit can be reduced as compared with the number of ICs capable of testing at the same time. Namely, if the number of ICs to be tested at the same time is increased, that the number of select signal is made to increase will do enough and can cope with a demand for low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a parallel interface that can be used, for example, in an IC testing device.

``Prior Art'' IC test equipment consists of a device called a handler that sequentially sends ICs under test to a measurement section and connects the ICs under test to an electric circuit, and a device that performs the work of connecting the ICs under test to an electric circuit in the handler. The main body of the tester determines whether the IC under test is a good product or a defective product by applying a pattern signal and checking whether the response output matches a predetermined expected value.

The handler is a mechanical device, whereas the tester body is an electronic circuit device. For this reason, the handler and the main body of the test device are placed apart, and signals are exchanged by connecting them with a cable.

This invention relates to an improvement of the parallel interface for receiving and receiving this signal.

FIG. 3 shows the configuration of a Halalel interface used in a conventional IC testing device. In the figure, 100 indicates a handler, and 200 indicates a tester body.

The figure shows the configuration of a parallel interface provided in the handler 100. Therefore, this configuration is also provided on the tester main body 200 side in a completely 1:1 correspondence.

Test request signals RQI-RQ shown in FIG. 4A are transferred from the handler lOO to the tester main body 200. These test request signals RQ, ~RQ are output when the IC under test is electrically connected to the measurement section, and are transferred to the tester main body 200 as a signal prompting the start of the test.

The reason why the test request signals RQ, .about.RQ, . Therefore, the number n of test request signals RQ, .about.RQ, corresponds to the number of measuring sections.

The test request signals RQ+ to PQ are taken into data latch circuits 10A to ION formed of circuits such as one-shot multivibrators, for example. The test request signals RQ1 to RQ taken into the data latch circuits 10A to IOH are outputted to the cable 12 through insulated transmission circuits 11A to 11N, such as photocouplers, and transmitted to the tester main body 200.

When the test period T shown in FIG. 4B has elapsed, the tester main body 200 sends back the judgment data D, ~D shown in the fourth rjllD through the data bus 14 to the handler 100,
Using the determination data D and -Dn, the handler 100 classifies the ICs under test into good and defective products and stores them in the storage section.

The determination data D1 to D are output on the data bus 14 in a time-division manner. This time-divided judgment data D
, ~D7 are launched into the launch circuits 13A~13N by the test end signal (FIG. 4C) TE~TE sent from the tester main body 200.

Note that 16A to 16N and 17 indicate isolated transmission circuits.

"Problem to be Solved by the Invention" Conventional parallel interfaces exclusively use one signal transmission line for one measurement section, so there is a drawback that the number of signal transmission lines increases as the number of measurement sections increases. .

In particular, in order to speed up testing, the number of measurement units is increasing, such as 4, 8, 16, 32, 64, and 128.

An increase in the number of signal transmission lines causes an increase in the scale of the circuit constituting the parallel interface and an increase in the number of core wires of the cable 12 connecting the handler 100 and the tester main body 200, which is uneconomical. Another disadvantage is that the increased diameter of the cable 12 makes it inconvenient to handle.

An object of the present invention is to provide a parallel interface that can reduce the number of signal transmission paths regardless of the number of measurement units provided in a handler.

"Means for Solving the Problem" In this invention, multiple data latch circuits that receive and receive parallel data are operated in a time-division manner over multiple time slots, and multiple sets of parallel data are processed using a common data latch circuit. It is designed so that it can be given and received.

According to the configuration of the present invention, in response to an increase in the number of measurement units, it is sufficient to increase the number of time slots, so it is possible to suppress an increase in the number of transmission paths. Therefore, an increase in the circuit scale of the interface can also be suppressed.

Therefore, even if the number of ICs that can be tested simultaneously is large, an advantage can be obtained that the IC testing apparatus can be manufactured at low cost.

"Example" In the first part, an example of the present invention will be shown. In the first session,
Portions corresponding to those in FIG. 3 are designated by the same reference numerals. In this embodiment, a configuration is shown in which 8 Ics can be tested simultaneously using 4-channel parallel transmission lines.

In other words, the four data latch circuits 10A to IOD have the second
As shown in Figure A, test request signals RQ to RQ, and RQs
~RQa is time-divided and input, and this test request signal RQ
, ~RQ s and RQ, ~RQ, l are sent from data latch circuits 10A to IOD to tester main body 200 through isolated transmission circuits 11A to LID in a time-division manner.

In order to define the time slots of the test request signals RQ, ~RQ, and RQS~RQ, in the present invention, from the handler 100 to the latch circuit 18, the isolated transmission circuit 19,
Block select signals BCI, , BC, z shown in the second diagram are sent through the buffer 20 to the task body 200 through the data bus 21.

The tester main body 200 uses block select signals BC, , and BC, □ to generate test request signals RQ, ~RQ, and R.
Identify and capture Qs to RQe.

When the test period T shown in FIG. 2B has elapsed, the tester main body 2
00 outputs the test end signals TE, ~TE, and T E s ~TE shown in FIG. 2C.

These test end signals TE, -TE, and TE, ~TE
s is input to the latch circuits 13A to 13D through the insulated transmission circuits 16A to 16D, and judgment data D1 to D4 and D shown in FIG. 2 are sent through the data bus 14.
5 to D are latched, respectively, and judgment data D1 to D are sent to the internal pass line 15.

and D5 to D.

In order to identify the judgment data D, -D, -D, the tester main body 200 sends block select signals BC and BC shown in the second figure to the data bus 21.

Output.

The handler 100 takes in the block select signals BC, , and BC2□ into the latch circuit 23 via the buffer 20 and the isolated transmission circuit 22, and uses the block select signals BC□ and BCtz launched into the latch circuit 23 to generate the judgment data D. , -D, and DsD.

"Effects of the Invention" As explained above, according to the present invention, data latch circuits 10A to 10D and 13A to 13D are operated in a time-division manner, and eight ICs are tested using four channels of signal transmission paths. Since it is configured to receive and receive data, the scale of the circuit can be reduced compared to the number of ICs that can be tested simultaneously.

Therefore, even if the number of ICs that can be tested simultaneously increases, the block select signal BC+5. BC+t and B CH
It is only necessary to increase the number of I, B Ctz, and it is possible to provide an IC testing device that can simultaneously test a large number of ICs at a low cost.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a waveform diagram for explaining its operation, Fig. 3 is a block diagram for explaining the conventional technique, and Fig. 4 is its operation. FIG. 2 is a waveform diagram for explaining. 100: Handler, 200; Tester body, 10A-1.
OD and 13A to 1.3D, 18, 23; Day latch circuit, IIA to LID and 1.6A to 16D I7
．． 19.22: Isolated transmission circuit.

Claims (1)

[Claims] (1) Multiple data latch circuits that receive and receive parallel data are time-divided and operated using multiple time throttles,
A parallel interface configured to receive and receive multiple sets of parallel data using a common data latch circuit.