JPH0425779A - Test mode setting circuit in semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide fail-safe effect without causing malfunction by unintentional signal input by making two systems of intermediate potential detecting means redundant, and deciding the results of the two intermediate potential detecting means and latching a test mode. CONSTITUTION:At least the two intermediate potential detecting means 2 and 3 detect an intermediate potential signal between a logic-1 level signal and a logic-0 level signal inputted from input terminals A and B used in common to input terminals for an internal circuit. Then an AND 6 detects whether the output signals of the means 2 and 3 are coincident with each other or not and its signal is latched by a latch means 4 to output a test mode setting signal C. Consequently, even if only one of the means 2 and 3 malfunctions owing to a noise, the test mode is not entered and when an intermediate potential is inputted first and the test mode is set, the intermediate potential need not be inputted thereafter; and normal logic signals are inputted to the input terminals to put the internal logic circuit 5 in operation.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a test mode setting circuit in a semiconductor integrated circuit including a logic circuit, etc., and particularly to a test mode setting circuit in a semiconductor integrated circuit that is improved to be less likely to malfunction. Regarding.

[Conventional technology] A conventional circuit is shown in FIG.

Description of circuit configuration: In FIG. 3, the semiconductor integrated circuit 1 is composed of an input terminal A, an internal logic circuit 5, an output terminal B, and intermediate potential detection means 2.

The intermediate potential detection means 2 includes a high level threshold inverter 2
1 and low level threshold inverter 22 and inverter 23
This is a test mode setting circuit consisting of AND24 and outputting a test mode setting signal.

FIG. 4 shows the relationship between the input voltages and logic levels of the inverters 21 to 23.

The signal input to input terminal A undergoes a predetermined logic operation in internal logic circuit 5 and is output to output terminal B.

A signal of a level different from a normal logic level signal (1 or 0) is input to the input terminal A.

In other words, if the logic input terminal and test mode setting signal input terminal are shared by input terminal A, and an intermediate potential signal (1/2 V) is input to input terminal A, the test mode setting circuit When the circuit is operated and a signal other than the intermediate potential is input, the normal internal logic circuit operates normally.

When the intermediate potential signal is input to the input terminal A, the high level threshold inverter 21 (
(threshold voltage>1/2 V) and low level threshold inverter 22 (threshold voltage <1/2 V).

When the high-level threshold inverter 21 receives an intermediate potential signal, the input potential is lower than the threshold voltage, so it is determined to be a logic level 0, the output is inverted, and a logic level 1 signal is generated by the AND24 is output to.

When the low-level threshold inverter 22 receives an intermediate potential signal, the input potential is higher than the threshold voltage, so it is determined to be a logic level 1, and the output is inverted to make a logic level 0 signal. It is output to the inverter 23.

The logic level O signal input to the inverter 23 is inverted and output to the AND 24.

AND24 performs an AND operation on the logic level 1 signal output from the high level threshold inverter 21 and the logic level 1 signal output from the inverter 23, and outputs an output signal C at logic level 1.

This output signal C is used as a test mode setting signal to the internal test circuit. If the output of AND24 is a logic level 0, the test mode is not entered.

The above describes the case where the test mode setting circuit 2 is operated in the test mode.

The high level threshold inverter 21 is determined to have a logic level 1 at its input, and therefore a logic output level 0 is determined by the AND24
Output to.

Low level threshold inverter 22 is determined to have a logic level 1 at its input, and therefore a logic output level 0 is output to inverter 23 .

Inverter 23 outputs logic output level 1 to AND 24 in response to logic input level O.

AND24 ANDs the logic input level 0 outputted from the high-level threshold inverter 21 and the logic input level 1 outputted from the inverter 23, so that a logic output level O is output.

In the above case, the logic output level is 0, so the test mode is not set. ■When logic level 0 is input; Output level 1 is AND24
Output to.

Low level threshold inverter 22 is determined to have a logic level 0 at its input, and therefore a logic output level 1 is output to inverter 23 .

The inverter 23 outputs a logic output level 0 to the AND 24 in response to a logic input level 1.

AND24 ANDs the logic input level 1 output from the high-level threshold inverter 21 and the logic input level 0 output from the inverter 23, so a logic output level 0 is output.

In the above case as well, as in the case of the test mode setting circuit input logic level input signal 1, the logic output level is O, so the test mode is not set.

Operation of the means: When the noise input voltage is 1/21 or more; the operation (2) above is executed and the test mode is not set.

When the noise input voltage reaches 1/2 (2), the operation (2) is executed and the test mode is set.

When the noise input voltage is 1/2 V or less: the operation (2) above is executed and the test mode is not set.

As described above, when noise passing through the intermediate potential and ranging from a high level to a low level is input to the intermediate potential detection means, the test mode is set unintentionally.

[Problems to be Solved by the Invention] The test mode setting circuit using the intermediate potential detecting means described above has the problem that impulsive noise, etc. that passes through the intermediate potential is inputted to the input terminal regardless of intention. If the internal logic circuit is used at normal logic level (1 or 0), the test mode setting circuit may malfunction in this way. It has been a major hindrance for users to put the inside of a semiconductor integrated circuit into a test mode.

Also, during the test mode, it is necessary to continue inputting an intermediate potential to the input terminal. Therefore, during this period, it is not possible to input a logic signal to the internal logic circuit to cause it to operate.

An object of the present invention is to provide a fail-safe effect so that a test mode setting circuit of a semiconductor integrated circuit does not malfunction even if an unintended signal such as noise is input to the test mode setting circuit.
An object of the present invention is to provide a test mode setting circuit capable of operating an internal logic circuit during test mode setting.

[Means for Solving the Problems] In view of the above-mentioned problems, the present invention has the following features:
The intermediate potential detection means of the conventional test mode setting circuit is made redundant at least twice, and the test mode setting is maintained by determining the results of the two intermediate potential detection means.

In other words, at least two intermediate potential detection means for detecting an intermediate potential signal between a logic 1 level signal and a logic 0 level signal input to two input terminals that are shared with the internal circuit input terminal; It is characterized by comprising: means for detecting coincidence/mismatch of signals output from the potential detection means; and latch means for latching the signal output from the coincidence/mismatch means and outputting a test mode setting signal as a latch output. shall be.

[Function] In the present invention, the intermediate potential detecting means is made redundant in two systems, and the test mode is latched by determining the results of the two intermediate potential detecting means, so that one of the two test mode setting circuits is Even if one test mode setting circuit malfunctions due to noise, it will not go into test mode.

Also, if you first input an intermediate potential to the input terminal and set the test mode, there is no need to input the intermediate potential to the input terminal after that, so you can input a normal logic signal to the input terminal and set the internal logic circuit. It is possible to perform the following actions.

[Example] The present invention will be explained in detail below.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

Circuit configuration description: In FIG. 1, the semiconductor integrated circuit 1 has input terminals A and B, which are shared as an input terminal for an internal logic circuit and an input terminal for a test mode setting circuit, and an output terminal CSD for an internal logic circuit.
, internal logic circuit 5, intermediate potential detection means 2 and 3, and A
It is composed of an ND6 and a latch 4.

Explanation of circuit operation: In FIG. 1, the intermediate potential detecting means 2 and 3 have the same circuit as the conventional intermediate potential detecting means 2, but their inputs are connected to two different input terminals A and B for internal logic circuits. be done.

Furthermore, the relationships between the input voltages and logic levels of the inverters 21 to 23 (31 to 33) are operated with the same definition as the relationship shown in FIG.

Therefore, the operation of the intermediate potential detecting means 2 and 3 is the same as in the prior art.

The logic output level signal output from the intermediate potential detection means 2.3 is output to AND6.

The logic output level signal detected as a match/mismatch by AND6 is output to the input 42A of the latch 4.

The latch 4 has an input/output relationship shown in the timing chart of FIG. ), the output of the NOR gate 42 becomes a logic output 1, and the output of the inverter 43 outputs a logic output level O (state 1 in FIG. 2).

The output signal C of this inverter 43 is at logic output level 1
When the logic output level is O (state 3.4 in FIG. 2), it indicates that the test mode is set, and when the logic output level is O (state 1.2 in FIG. 2), it indicates that the test mode is not set.

0 is output to the AND6 output when the input voltage of the input terminal ASB is a voltage other than the intermediate voltage 1/2 V and the test mode is not set, and 1 is output to the AND6 output. When the input voltages of input terminals A and B are the intermediate voltage]/2V, it is time to set the test mode.

When the logic input terminal and the test mode setting signal input terminal are shared by the input terminal ASB, and an intermediate potential signal (1/2 V) is input to the input terminal ASB, the intermediate potential detection means 2.3 is operated and a signal other than the intermediate potential is input, the normal internal logic circuit operates normally.

Further, one pulse of an internal reset signal (logic input level 1) such as a power-on reset signal is input to the input 41A.

When an intermediate potential signal is input to the input terminal ASB, the high level threshold inverter 2 of the intermediate potential detecting means 2 and 3
1 (threshold voltage > 1/2 V) (31) and low-level threshold inverter 22 (threshold voltage < 1/2 V)
) (32).

When the high-level threshold inverter 21 (31) receives the intermediate potential signal, the input potential is lower than the threshold voltage, so it is determined to be at logic level O, and the output is inverted to signal logic level 1. is output to AND24 (34).

When the low-level threshold inverter 22 (32) receives an intermediate potential signal, the input potential is higher than the threshold voltage, so it is determined to be logic level 1, and the output is inverted to the logic output level. 0 is output to the inverter 23 (33).

Logic level O input to inverter 23 (33)
The signal is inverted and output to AND24 (34).

AND24 (34) performs AND24 (34) of the logic level 1 signal output from the high level threshold inverter 21 (31) and the logic level 1 signal output from the inverter 23 (3B). , two logic level 1 output signals are output to AND6.

If the output signals match, a logic output level 1 of AND6 is output to input 42A of latch 4.

At this time, the state of the latch 4 corresponds to state 3 in FIG. 2, and the test mode is set.

Next, a logic level 1 other than the intermediate potential is applied to input terminal A or B.
Or, even if O is input and a logic level 0 is output from the AND6 output to the latch 42A, the latch output maintains state 4 in FIG. 2 and continues the test moto setting.

Therefore, as in the past, the test mode setting internal terminal A,
There is no need to continue inputting an intermediate potential to H.

The above describes the case where the test mode setting circuit 7 is operated in the test mode.

To end the test mode, by inputting the reset signal (logic level 1) again to the input 41A, state 5 in FIG. 2 is established, and the test mode is ended.

Next, when there is a power-on reset to the input 41A of the latch 4; ■When a logic level 1 is input;
It is output to AND24 (34).

The low level threshold inverter 22 (32) is determined to have a logic level 1 at its input, so that its logic output level O is
It is output to the inverter 23 (3B).

The inverter 23 (33) outputs a logical output level 1 to the AND24 (34) with respect to the logical human power level 0.

AND24 (34) ANDs the logic input level 0 output from the high-level threshold inverter 21 (31) and the logic input level 1 output from the inverter 23 (C33), so the logic output level 0 is AND6
is output to.

AND6 has two logic input levels of 0, so A
An ND logic output level 0 is output to latch 42A.

At this time, the state of the latch 4 corresponds to state 2 shown in FIG. 2, so the test mode setting is not established.

(2) When logic level 0 is input; The high level threshold inverter 21 (31) determines that the input is logic level 0, and therefore outputs logic output level 1 to AND24 (34).

The low level threshold inverter 22 (32) is determined to have a logic level 0 at its input, so that its logic output level 1 is
It is output to the inverter 23 (33).

Inverter 23 (33) outputs logic output level 0 to AND24 (34) in response to logic input level 1.

AND24 (34) is the logic input level 1 output from the high level threshold inverter 21 (31) and the logic input level 0 output from the inverter 23 (33).
are ANDed, so the logical output level 0 is AND6
is output to.

AND6 has two logic input levels of 0, so A
ND logic output level 0 is output to latch 42A.

At this time, the state of the latch 4 corresponds to state 2 shown in FIG. 2, so the test mode setting is not established.

Since the operation (2) is executed in the intermediate potential detection means 2, the test mode is not set regardless of the signal input to the input terminal B.

When the input voltage of the noise reaches 1/2 V; the above operation (■) is executed in the intermediate potential detection means 2, and when the voltage of 1/2 V is simultaneously input to the input terminal B, the test mode is set. However, 1/1 is applied to input terminal B.
If a voltage other than 2 V is input, test mode will not be set.

Since there is almost no probability that the same voltage is input to the input terminal ASB at the same time, the test mode is never set.

When the noise at the input terminal is 1/2 V or less; the intermediate potential detecting means 2 executes the operation (2), so the test mode is not set regardless of the signal input to the input terminal B.

If noise is input to input terminal B, the same result as the above operation will be obtained.

As mentioned above, the test mode setting circuit passes through the intermediate potential and the noise ranging from high level to low level is input to the input terminal A.
Or even if it is input to B, the test mode is not set.

However, if signals with the same waveform are input to the input terminals A and B at the same time, the test mode will be set, but since this frequency is almost non-existent in terms of probability, the test mode will not be set.

In this embodiment, two intermediate potential detection means are provided, but the present invention is not limited to two, and even if three or more are provided, the same operation will be performed, and the frequency of malfunctions will further be reduced.

[Effects of the Invention] As explained above, according to the present invention, it is necessary to add some circuits to the semiconductor integrated circuit for the test mode setting circuit. After that, by inputting a test logic signal to the input terminal, test
In addition, when the internal logic circuit of a semiconductor integrated circuit is normally used, the test mode setting circuit may malfunction due to noise etc., which may affect the operation of the internal logic circuit. This will greatly reduce the amount of worry you have to worry about.

Therefore, it is clear that the present invention will make a significant contribution to improving and maintaining the reliability and quality of semiconductor integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
A timing chart of the latch 4, FIG. 3 is a circuit diagram showing a conventional embodiment, FIG. 4 is a definition of the input voltage and logic level of the inverters 21 to 23, and FIG. 5 is a diagram of a noise signal. . 1 ... Semiconductor integrated circuit 2.3 ... Intermediate potential detection means 4 ... Latch means 5 ... Internal logic circuit 6 ... AND 7 ... Test mode setting circuit 21.31 ... High Level threshold inverter 2
2.32 ... Low level threshold inverter 2B
, 33.43 ... Inverter 24.34
... AND 41.42 ... NOR

Claims (1)

[Claims] In a semiconductor integrated circuit including an input terminal, a logic circuit, an output terminal, and a test mode setting circuit that generates a test mode signal for the internal logic circuit, two Two intermediate potential detection means for detecting an intermediate potential signal between a logic 1 level signal and a logic 0 level signal input to the input terminal; and detecting coincidence/mismatch of signals output from the two intermediate potential detection means. A test mode setting circuit in a semiconductor integrated circuit, comprising: means for latching a signal output from the match/mismatch means and outputting a test mode setting signal as a latch output.