JPH04258004A - Amplifier circuit - Google Patents

Abstract

PURPOSE:To operate the amplifier circuit stably over a wide range of a power supply voltage and a gate potential by devising the amplifier circuit to absorb a fluctuation of an operating point of the amplifier circuit due to fluctuation of the power supply voltage and a gate bias potential. CONSTITUTION:The amplifier circuit consists of a MOS field effect transistor(TR) (N-channel MOD TR M1) and a load element (N-channel MOSTR M2) connected in series between a power terminal and a ground terminal. Then an inversed signal to either a signal at a connecting point between the MOSFET and the load element or its equivalent signal is inputted to a gate of the N- channel MOS TR via a resistive element R3 to drive the gate of the MOS TR being a component of the amplifier circuit is driven by a bias potential generated by a self-bias type bias voltage generating circuit.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit, and more particularly to a circuit configuration of a source follower type amplifier circuit in which a bias level is automatically set.

0002

2. Description of the Related Art FIG. 4 shows an equivalent circuit diagram of an example of a conventional amplifier circuit of this type. This amplifier circuit is an N-channel MO
It consists of an S transistor N, a resistor R1, a resistor R2, an inverting amplifier 1, and a constant voltage source 2.

The N-channel MOS transistor N has a drain connected to a power supply terminal and a source grounded via a resistor R1. A constant bias potential VG is applied to the gate from a constant voltage source 2 via a resistor R2.

In reality, the gate bias potential VG is substituted with the power supply potential, or if the N-channel MOS transistor N is a depletion type, the gate of this MOS transistor is connected to the source. .

[0005] In the above amplifier circuit, an N-channel MOS
The gate of transistor N serves as an input, and the source serves as an output. The inverting amplifier 1 is for waveform shaping.

As is generally well known, such an amplifier circuit has the characteristics of a voltage gain of 1 or less and a relatively low output impedance.

[0007]

In order to operate the conventional amplifier circuit described above, it is necessary to bias the gate of the N-channel MOS transistor N to a point where the output potential satisfies the following conditions. 0<R1 ・IN<VDD-VTN

(1) R1 ・IN ≒VTI

(2) However, IN is the current flowing through the N-channel MOS transistor N when the gate bias potential is VG, and V
TN is the threshold voltage of this MOS transistor. Further, VTI is the logic threshold of the inverting amplifier 1.

[0008] Now, considering the case where the power supply voltage VDD and the gate bias potential VG increase, the current flowing through the MOS transistor increases in proportion to the square of (VG - VTN). The value of the central term becomes large and this inequality can no longer be satisfied.

On the other hand, the logical threshold value VTI of the inverting amplifier 1
In other words, since the logic threshold of an inverting amplifier having a CMOS configuration is proportional to a change in the power supply voltage, it becomes impossible to satisfy equation (2).

Conversely, the power supply voltage and gate bias potential V
When G becomes low, the term on the right side of equation (1) approaches 0 earlier than the left side, so equation (1) cannot be satisfied. Also, for the same reason as mentioned above, (
2) will no longer be satisfied.

As described above, conventional amplifier circuits have problems in operating over a wide range of power supply voltages and gate bias potentials.

0012

[Means for Solving the Problems] In the amplifier circuit of the present invention,
A self-bias type bias voltage generation circuit is provided to absorb fluctuations in the power supply voltage and gate bias potential.

The amplifier circuit of the present invention includes a MOS field effect transistor and a load element connected in series between a power supply terminal and a ground terminal. The present invention is characterized in that an inverted signal of either a signal at a connection point between the transistor and the load element or a signal equivalent to this signal is inputted via a resistance element.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention.

In this embodiment, N-channel MOS transistors M1 and M2 are connected in series between the power supply and ground, and an N-channel MOS transistor with similar characteristics is connected in series between the power supply and ground.
S transistors M3 and M4 are similarly connected in series between the power supply and ground.

The N-channel MOS transistors M2 and M4 on the ground side have their respective gates connected in common, and are further connected to the drain of the N-channel MOS transistor M4.

The potential of the drain of this N-channel MOS transistor M4 is inverted by an inverting amplifier 3 and supplied to the gate of the N-channel MOS transistor M3. This inverted level potential is also applied to the N-channel MOS transistor M1 via the bias resistor R3.
The gates are also supplied.

In the amplifier circuit of this embodiment, N-channel M
The gate of OS transistor M1 becomes the input, and this M
The source side of the OS transistor serves as an output. The inverting amplifier 1 is for waveform shaping.

The circuit operation of this embodiment will be described below.

In FIG. 1, a circuit composed of N-channel MOS transistors M3 and M4 and an inverting amplifier 3 is a self-bias type bias voltage generation circuit.

First, the potential of the input of the inverting amplifier 3 is set to Vin.
, the output potential is Vout, and the threshold voltage of N-channel MOS transistor M3 is VTM3, then N-channel MOS transistors M1 and M3 are set at Vin
=Vout-VTM3.

In this state, as shown in FIG. 2, since the inverting amplifier 3 is always biased at a certain gain, the waveform of the inverting amplifier 1 having the same input/output characteristics as that of the inverting amplifier 3 is When used for shaping, the input signal is reliably converted into a clock signal for logic circuits.

It should be noted that when the power supply voltage becomes low, the inverting amplifier 3 cannot obtain sufficient gain, but as long as the DC gain is 1 or more, there is no problem as a bias voltage generating circuit.

At this time, a differential amplifier is used for waveform shaping, and N-channel MOS transistors M2 and M
Make the drain side of 4 the respective differential input.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a circuit diagram of a second embodiment of the present invention. In this embodiment, a depletion type N-channel MOS transistor M5 whose gate is grounded is arranged on the ground side, an N-channel MOS transistor M1 is arranged on the power supply side, and these MOS transistors are connected in series.

In this embodiment, the connection point between the above two MOS transistors is the output, and the potential of this output is inverted by the inverting amplifier 3 and biases the gate of the N-channel MOS transistor M1 via the bias resistor R3. ing. And this N channel MOS transistor M
The gate of 1 is the input of this amplifier circuit.

Note that the inverting amplifier 1 connected to the output of this amplifier circuit is for waveform shaping.

In this embodiment, as in the first embodiment, an inverted level of the output is created, thereby obtaining a bias potential. Therefore, the circuit operates similarly to the first embodiment.

The difference between this embodiment and the first embodiment shown in FIG. 1 lies in the output load. In the first embodiment, the output load is a current source made of a current mirror circuit, and three MOS transistors are required for this, whereas in this embodiment, a depletion type MOS transistor M5 1 It has been simplified into pieces.

In addition to the above, this depression type M
A resistive element can also be used instead of the OS transistor.

It is also possible to configure the bias resistor R3 with a MOS transistor.

[0033]

As explained above, the present invention enables the amplifier circuit to be controlled by the power supply voltage and the gate potential by driving the gates of the MOS transistors constituting the amplifier circuit with the bias potential generated by the self-bias circuit. It has the effect of being able to operate stably over a wide range.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a diagram showing the input/output characteristics of the inverting amplifier in the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a second embodiment of the invention.

FIG. 4 is a circuit diagram of a conventional amplifier circuit.

[Explanation of symbols]

1 Inverting amplifier 2 Constant voltage source 3 Inverting amplifier

Claims (1)

[Claims] 1. Consisting of a MOS field effect transistor and a load element connected in series between a power supply terminal and a ground terminal, the gate of the MOS field effect transistor includes:
An amplifier circuit characterized in that an inverted signal of either a signal at a connection point between the MOS field effect transistor and the load element or a signal equivalent to this signal is inputted via a resistance element.