JPH04258016A - Switched capacitor circuit - Google Patents

Abstract

PURPOSE:To suppress voltage discontinuity in an output signal and to prevent an undesired overshoot or ringing or the like by inserting a charge transfer analog delay circuit between an input signal and a switch circuit so as to provide a delay time to the input signal thereby applying nearly the same voltage as a voltage used for a voltage at the discrimination of the quantity between the input signal and a reference signal in a switched capacitor comparator to the switch circuit. CONSTITUTION:The title circuit is provided with a switched capacitor comparator 1 discriminating the quantity of the level between an input signal 101 and a reference signal 102, a delay circuit 2 delaying an output signal by a prescribed time and outputting the delayed signal, a charge transfer analog delay circuit 6 delaying the input signal 101 by a prescribed time and outputting the delayed signal, and a switch circuit controlled by a switching control signal 106 outputted via the delay circuit 2, a D flip-flop 3 and a control circuit 4, receiving an output signal of the charge transfer analog delay circuit and the reference signal 102, selecting and outputting any of them.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switched capacitor circuit, and more particularly to a switched capacitor circuit that performs switching based on an output control signal of a switched capacitor type comparator.

0002

2. Description of the Related Art A conventional switched capacitor circuit has an operational amplifier 1 as shown in FIG.
1, a switched capacitor type comparator 1 including switches 12 to 14 and a capacitor 15, a delay circuit 2, and D
The device includes a type flip-flop 3, a control circuit 4, and a switch control circuit 5. Here, regarding the components of the switched capacitor type comparator 1, the switch 12 is a switch that is turned on at the timing of the clock signal 132, and the switches 13 and 14 are each turned on at the timing of the clock signal 133.
This is a switch for N. Further, the capacitor 15 is a capacitor for storing charge, and the operational amplifier 11 has a function of determining whether the charge stored in the capacitor 15 is positive or negative.

In FIG. 4, an input signal 130 and a reference signal 131 are connected to a switched capacitor type comparator 1.
and is input to the switch circuit 5. In the switched capacitor type comparator 1, the magnitude relationship between the input signal 130 and the reference signal 131 is determined, and the determined output signal is passed through the delay circuit 2 to the D of the D-type flip-flop 3.
A signal synchronized with the clock signal 134 (inverted clock signal of the clock signal 132) input to the C terminal of the D-type flip-flop 3 is output and input to the control circuit 4. A switch switching control signal 135 is output from the control circuit 4 and input to the switch circuit 5. This switch switching control signal 135 is output with a delay of at least one clock after determining the magnitude relationship between the input signal 130 and the reference signal 131 at a time nT. That is, in the switch circuit 5, the time required to switch the switch is at least (n
+1) After time T.

On the other hand, since the input signal 130 input to the switch circuit 5 changes in level between time nT and time (n+1)T, the output signal 136 of the switch circuit 5 is The level changes continuously from the time nT at which the switch is made to the time (n+1)T at which the switch is actually made. In this case, clock signal 1
32, 133, a time chart showing the state of the input signal 130, reference signal 131 and output signal 136 is shown in FIG.
Shown in a), (b), (c) and (d).

[0005]

[Problems to be Solved by the Invention] In the conventional switched capacitor circuit described above, the time required to determine the magnitude of the level of the input signal and the reference signal in the switched capacitor type comparator and the time required to actually switch Since there is a delay time synchronized with the clock signal between the control time and the control time, the level of the input voltage changes at the output of the switch circuit during the delay time, as shown in FIG. 6(c). This has the drawback that a discontinuous portion occurs in terms of voltage, and the symmetry of the rise and fall of the input signal is lost.

[0006]

Means for Solving the Problems The switched capacitor circuit of the present invention, in response to the input of a predetermined input signal and a reference signal, outputs the input signal and the reference signal via first and second clock signals. a switched capacitor type comparator that determines the magnitude of the level of the switched capacitor type comparator; a delay circuit that delays and outputs the output signal of the switched capacitor type comparator by a predetermined time; the output signal of the delay circuit is inputted to the D terminal; A D-type flip-flop receives an inverted clock signal of the first clock signal from its C terminal and outputs a signal synchronized with the inverted clock signal of the second clock signal from its Q terminal; a control circuit that inputs an output signal and outputs a predetermined switch switching control signal; A charge transfer type analog delay circuit for delayed output, an output signal of the charge transfer type analog delay circuit, and the reference signal are input, and one of them is selected and outputted via the switch switching control signal. and a switch circuit.

[0007]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, this embodiment includes a switched capacitor type comparator 1 including an operational amplifier 11, switches 12 to 14, and a capacitor 15, a delay circuit 2, a D-type flip-flop 3, and a control circuit 4. , a switch circuit 5 , and a charge transfer type analog delay circuit 6 . Here, regarding the components of the switched capacitor type comparator 1, as in the case of the conventional example, the switch 12 is a switch that is turned on at the timing of the clock signal 103, and the switches 13 and 14 are switches that are turned on at the timing of the clock signal 104. O in timing
This is a switch for N. Further, the capacitor 15 is a capacitor for storing charge, and the operational amplifier 11 has a function of determining whether the charge stored in the capacitor 15 is positive or negative.

In FIG. 1, an input signal 101 is input to a switched capacitor type comparator 1 and a charge transfer type analog delay circuit 6. Further, the reference signal 102 is input to the switched capacitor type comparator 1 and the switch circuit 5. In the switched capacitor type comparator 1, the magnitude relationship between the input signal 130 and the reference signal 131 is determined as in the case of the conventional example, and the determined output signal is sent to the D-type flip-flop 3 via the delay circuit 2. A signal input to the D terminal and synchronized with the clock signal 105 (an inverted clock signal of the clock signal 104) input to the C terminal of the D-type flip-flop 3 is output and input to the control circuit 4. A switch switching control signal 106 is output from the control circuit 4 and input to the switch circuit 5.

On the other hand, in the charge transfer type analog delay circuit 6, charge is transferred to the input signal 101 via the clock signals 103 and 104. The time from the time to determine the magnitude relationship between the signal number 101 and the reference signal 102 until it is output as the switch changeover control signal 106 from the control circuit 4 via the delay circuit 2, the D-type flip-flop 3, and the control circuit 4. Make it the same as time. Input signal 101 at level judgment time in switched capacitor type comparator 1
The voltage level appears as the output of the charge transfer type analog delay circuit 6 after a time tT. In this case, clock signals 103, 104, input signal 101,
Time charts showing the state of the reference signal 102 and the output signal 107 are shown in FIGS. 5(a), (b), (c) and (d).
) is shown. Therefore, in this embodiment, the discontinuous voltage level range in the output signal 107 is suppressed, and the apparent amount of overshoot is reduced. Input signal 101
However, in the case of a waveform that is sampled and held at the timing of the clock signal 103 or 104, the effect of reducing the amount of overshoot becomes even greater.

FIG. 2 shows an example in which the present invention is applied to a mute circuit. As shown in FIG. 2, this mute circuit includes two circuit systems including a switched capacitor type comparator 1, a delay circuit 2, and a D-type flip-flop 3.
As a circuit element common to the circuit system of the system, a control circuit 4,
A charge transfer type analog delay circuit 6, a switch circuit 5, and an adder circuit 7 are provided.

In FIG. 2, an input signal 108 is commonly input to two systems of switched capacitor type comparators 1 and charge transfer type analog delay circuits 6. Further, the reference signals 109 and 110 are individually input to the two switched capacitor type comparators 1, respectively. In the switched capacitor type comparator 1 in each system, as in the case of the conventional example, the input signal 108, the reference signal 109, and the input signal 108
The magnitude relationship between the reference signal 110 and the reference signal 110 is individually determined, and the determined output signals are input to the common control circuit 4 via the respective delay circuits 2 and D-type flip-flops 3. Switch switching control signals 116 and 117 are output from the control circuit 4 and input to the switch circuit 5. The switch circuit 5 is formed of a pair of switches 16 and 17, and these switches are controlled and operated by the above-mentioned switch changeover control signals 116 and 117, respectively.

On the other hand, in the charge transfer type analog delay circuit 6, charge is transferred to the input signal 108 via the clock signals 112 and 113, but the charge transfer time is determined by each system as in the previous embodiment. In the switched capacitor type comparator 1, the input signal 108 and the reference signal 109, or the input signal 108 and the reference signal 11
It is the same as the time from the time for determining the magnitude relationship with 0 to the time for outputting the switch switching control signal 116 or 117 from the control circuit 4 via the delay circuit 2, the D-type flip-flop 3, and the control circuit 4. do. The input signal delayed in the charge transfer type analog delay circuit 6 is input to the switch 16 of the switch circuit 5, but the other switch 17 of the switch circuit 4 is connected to a reference voltage 111 (usually a ground potential). ing. By setting the switch circuit 5 to operate when the level of the input signal 108 is higher than the reference signal 109 and lower than the reference voltage 110, this circuit functions as a mute circuit. In this mute circuit, in order to maintain symmetry in the rise and fall of the input signal 108, the charge transfer type analog delay circuit 6 delays the input waveform as a whole.

FIG. 3 shows an example in which the present invention is applied to a limiter circuit. As shown in FIG. 3, this limiter circuit includes two circuit systems including a switched capacitor type comparator 1, a delay circuit 2, and a D-type flip-flop 3.
As a circuit element common to the circuit system of the system, a control circuit 4,
A charge transfer type analog delay circuit 6, a switch circuit 5, and an adder circuit 7 are provided.

In FIG. 3, an input signal 119 is commonly input to two systems of switched capacitor type comparators 1 and charge transfer type analog delay circuits 6. Also, a high level reference signal 120 and a low level reference signal 1
21 are individually input to the two systems of switched capacitor type comparators 1. In the switched capacitor type comparator 1 in each system, the magnitude relationship between the input signal 119 and the high level reference signal 120, and between the input signal 119 and the low level reference signal 121 is determined individually, as in the case of the conventional example. , the determination output signals thereof are input to a common control circuit 4 via respective delay circuits 2 and D-type flip-flops 3. Switch switching control signals 126, 127 and 128 are output from the control circuit 4 and input to the switch circuit 5. The switch circuit 5 is formed of three sets of switches 18, 19, and 20, and these switches each receive the above-mentioned switch changeover control signal 12.
6, 127 and 128.

On the other hand, in the charge transfer type analog delay circuit 6, charge is transferred to the input signal 119 via the clock signals 122 and 123, and the charge transfer time is determined by each system as in the previous embodiment. In the switched capacitor type comparator 1, from the time to determine the magnitude relationship between the input signal 119 and the high level reference signal 120, or the input signal 119 and the low level reference signal 121,
Delay circuit 2, D-type flip-flop 3 and control circuit 4
A switch switching control signal 12 is sent from the control circuit 4 via
It is set to be the same as the time until it is output as 6, 127, or 128. The input signal delayed in the charge transfer analog delay circuit 6 is input to the switch 19 of the switch circuit 5, but the other switches 18 and 20 of the switch circuit 4 receive a high level reference signal 120 and a low level reference signal, respectively. Signal 121 is connected. In the switch circuit 5, the level of the input signal 119 is higher than the high level reference signal 109, lower than the low level reference signal 110, or is at an intermediate level between the high level reference signal and the low level reference signal. , a type of limiter circuit is configured in which it is specified whether to select an input signal, a high level reference signal, or a low level reference signal as an output signal. In this limiter circuit, by delaying the input signal 119 itself in the charge transfer type analog delay circuit 6, ringing that occurs when the limiter is sensed can be prevented.

[0017]

As explained above, the present invention inserts a charge transfer type analog delay circuit between the input signal inputted to the switched capacitor type comparator and the switch circuit, thereby providing an appropriate response to the input signal. By providing a delay time, it is possible to input almost the same voltage value to the switch circuit as the voltage value when determining the magnitude of the input signal and the reference signal in the switched capacitor type comparator. This has the effect of suppressing voltage discontinuity and preventing unnecessary overshoot or ringing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a mute circuit as an application example of the present embodiment.

FIG. 3 is a block diagram showing a limiter circuit as an application example of the present embodiment.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a diagram showing operational waveforms in this embodiment.

FIG. 6 is a diagram showing operating waveforms in a conventional example.

[Explanation of symbols]

1 Switched capacitor type comparator 2
Delay circuit 3 D-type flip-flop 4 Control circuit 5 Switch circuit 6 Charge transfer type analog delay circuit 7 Addition circuit 11 Operational amplifier

Claims (1)

[Claims] 1. In response to input of a predetermined input signal and a reference signal, via first and second clock signals,
a switched capacitor type comparator that determines the magnitude of the level of the input signal and the reference signal; a delay circuit that delays the output signal of the switched capacitor type comparator by a predetermined time and outputs the output signal;
a D-type flip-flop that receives an inverted clock signal of the first clock signal from a C terminal and outputs a signal synchronized with the inverted clock signal of the second clock signal from a Q terminal; a control circuit that inputs the output signal of the D-type flip-flop and outputs a predetermined switch switching control signal; and a control circuit that inputs the predetermined input signal and synchronizes with the first and second clock signals, A charge transfer type analog delay circuit that delays the input signal by a predetermined time and outputs the same; an output signal of the charge transfer type analog delay circuit; and the reference signal; A switched capacitor circuit comprising: a switch circuit that selects and outputs one of the two.