JPH04258018A - Amplitude conversion circuit - Google Patents

Abstract

PURPOSE:To quicken the circuit operation without increasing a current consumption by short-circuiting an impedance element inserted to emitter terminals of transistors(TRs) constituting of a differential amplifier circuit with an analog switch. CONSTITUTION:The conversion circuit consists of a differential amplifier circuit 1 comprising TRs and main and auxiliary load resistors R1,R2, transmission gates 2,3, inverter circuits 4,5, a constant current source supplying the operating current of the differential amplifier circuit 1, a power supply V1 and a bias power supply V2 of the TR. The transmission gates use complementary pulses so as to control each gate of the P-channel MOS TRs and N-channel MOS TRs to be conductive or nonconductive respectively. That is, two TRs being components of the differential amplifier circuit 1 act like common base amplifiers. Thus, the production of a delay due to stray capacitance is reduced to a negligibly small degree.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplitude conversion circuit, and more particularly to an amplitude conversion circuit that converts the amplitude of a logic signal of a CMOS logic circuit to the amplitude of a logic signal of an ECL logic circuit.

0002

2. Description of the Related Art A conventional amplitude conversion circuit, as shown in FIG.
1 and R2, an attenuation circuit 7 including resistors R3 to R5, a bias circuit 8 including resistors R6 and R7, and a constant current source I1 that supplies the operating current of the differential circuit 1.
By reducing the amplitude of the logic signal of the CMOS logic circuit 6, it is converted into the amplitude of the logic signal of the ECL logic circuit.

Next, the operation of the conventional amplitude conversion circuit will be explained.

The attenuation circuit 7 functions to reduce the amplitude of the output signal of the CMOS logic circuit 6. The differential circuit 1, load resistors R1 and R2, and constant current source I1 constitute a buffer for the ECL logic circuit. Terminal TO, TOI
are the positive phase output terminal and complementary phase output terminal, respectively, and EC
A signal converted into a signal with an appropriate amplitude is output to the L logic circuit. The bias circuit 8 is for supplying a DC bias to the transistor Q2 of the differential circuit 1.

First, it is assumed that the voltage of the power supply V1 is V1, and the output resistance of the output circuit of the CMOS logic circuit 6, that is, the on-resistance of the output transistor is r. FIG. 3(a) shows an equivalent circuit when the output of the CMOS logic circuit 6 applied to the attenuation circuit 7 consisting of resistors R3 to R5 is at a high level. Base potential V of transistor Q1 of differential circuit 1 in this case
AH is expressed by the following formula.

[0006]

Next, FIG. 3(b) shows an equivalent circuit when the output of the CMOS logic circuit 6 applied to the attenuation circuit 7 is at a low level. The base potential VAL of the transistor Q1 of the differential circuit 1 in this case is expressed by the following equation.

[0008]

As a concrete numerical example, V1=5V, r=
3KΩ, R4=R5=20KΩ, R3=40KΩ, VAH=2.94V, VAL=2.06V,
A signal amplitude of about 1V centered around 2.5V will be obtained. Therefore, the resistances R6 and R7 of the bias circuit 8 are
For example, R4/R5=R6/R7………………………………
By selecting as in (3), the transistors Q1 and Q2 of the differential circuit 1 conduct conduction and cutoff operations alternately, and the current value of the constant current source I1 and the load resistance The signal amplitude determined by the resistors R1 and R2 is outputted from the correction output terminals TO and TOI.

0010

[Problems to be Solved by the Invention] In the conventional amplitude conversion circuit described above, the input impedance at the input terminal of the differential circuit is high due to the attenuation circuit consisting of a resistor network, so even the presence of a small amount of stray capacitance causes a significant delay. However, it has the disadvantage of reducing the operating speed.

In the above numerical example, this input impedance is 8.1KΩ, and even with a stray capacitance of about 1pF, the input impedance is about 8.1KΩ.
Generates a delay of nS. In order to reduce this input impedance, it is possible to reduce the resistance value of the resistor that makes up the attenuation circuit, but this results in an increase in current consumption, which is a trade-off between operating speed and current consumption. There was a point.

0012

[Means for Solving the Problems] The amplitude conversion circuit of the first invention comprises first and second transistors forming a differential circuit and outputting respective output signals of correction and correction, and an operating current of the differential circuit. and first and second analog switch circuits connected between the constant current source and the emitters of each of the first and second transistors, each having an impedance element connected in parallel; , and a switch control circuit that complementarily controls the first and second analog switch circuits to conduct or cut off, respectively.

[0013]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the amplitude conversion circuit of the present invention.

As shown in FIG. 1, the amplitude conversion circuit of this embodiment includes a differential circuit 1 consisting of transistors Q1 and Q2 and corrective load resistances R1 and R2, transmission gates 1 and 2, Inverter circuits 4 and 5, a constant current source I1 that supplies the operating current of the differential circuit 1, and a power supply V1,
It consists of a bias power supply V2 for transistors Q1 and Q2. FIG. 1 further shows a CMOS logic circuit 6, which is an input signal source, as in the conventional example, for the sake of explanation.

As is well known, the transmission gate is composed of a P-channel MOS transistor and an N-channel MOS transistor.
This is an analog switch in which the drain-in and source of each OS transistor are connected in common, and each gate is controlled to be conductive or cut-off by pulses of complementary polarity.

The transmission gate 1 is composed of a P-channel MOS transistor P1 and an N-channel MOS transistor N1, and is connected between the emitter of the transistor Q1 of the differential circuit 1 and a constant current source I1, and further includes an impedance element Z1. are connected in parallel.

The transmission gate 2 is composed of a P-channel MOS transistor P2 and an N-channel MOS transistor N2, and is connected between the emitter of the transistor Q2 of the differential circuit 1 and the constant current source I1, and further includes an impedance element Z2. are connected in parallel.

Impedance elements Z1 and Z2 are, for example, resistances that are sufficiently larger than the conduction resistance of transmission gates 1 and 2.

The inverter circuit 4 is a P-channel MOS
Transistor P3, N channel MOS transistor N
3, it inverts the input signal from the CMOS logic circuit 6 and inputs it to the inverter circuit 5, and also drives this as a positive drive signal for one of the transmission gates 1 and 2.

The inverter circuit 5 is a P-channel MOS
Transistor P4, N channel MOS transistor N
4, the signal from the inverter circuit 4 is further inverted and used as the other positive drive signal for the transmission gates 1 and 2.

Next, the operation of this embodiment will be explained.

First, a drive signal from the inverter circuit 4 is applied to the gates of the N-channel MOS transistor N1 of the transmission gate 1 and the P-channel MOS transistor P2 of the transmission gate 2. At the same time, transmission gate 1
P-channel MOS transistor P1 of the transmission gate 2 and N-channel MOS transistor N2 of the transmission gate 2
A drive signal from the inverter circuit 5 is applied to each gate. As described above, the polarities of the outputs of the inverter circuits 4 and 5 are mutually inverted, so when one of the transmission gates 1 and 2 is conductive, the other is necessarily cut off.

As in the conventional example, the operation will be explained using mathematical formulas.

[0025] Here, it is assumed that impedance elements Z1 and Z2 are resistors of the same value, and that value is set as RE. Also,
P-channel MOS transistor and N-channel M
If the conduction resistance of each OS transistor is r,
The conduction resistance of each of transmission gates 1 and 2 is 1/2r. Furthermore, it is assumed that RE is a much larger value than r.

First, when the output of the inverter circuit 4 is high level and the output of the inverter circuit 5 is low level, the transmission gate 1 becomes conductive and the transmission gate 2 becomes cut off. Therefore, impedance element Z1 is short-circuited at r/2. Therefore, a resistor of approximately r/2 is inserted into the emitter of the transistor Q1 of the differential circuit 1.

At this time, the collector current of transistor Q1 is IC1, and the collector current of transistor Q2 is IC1.
2 and the current of the constant current source I1 is I1, there is a relationship between these currents as shown in the following equation.

IC1+IC2=I1……………………………………
………………………(4)

[0029]

Here, RE=60KΩ, r=3KΩ, I
If 1=200μA, from equations (4) and (5),
IC1・r/2−(I1−IC1)・RE=0……
………………………(6) From this, IC1=19
5μA, IC2=5μA.

[0031] The values of resistances R1 and R2 of the load resistance are R5=
If R6 = 2KΩ, the potential of the terminal TO is the power supply voltage V1
The potential of the terminal TOI is V1-390 mV, and the potential of the terminal TOI is V1-10 mV. Next, when the output of the inverter circuit 5 is high level and the output of the inverter circuit 4 is low level, the transmission gate 2 becomes conductive and the transmission gate 1 becomes cut off. In this case, contrary to the previous case, the terminal TO
The potential of I is V1-390m with respect to the potential of power supply voltage V1.
V, and the potential of the terminal TO is V1-10 mV. As a result of the above, a signal amplitude of 380 mVP-P can be obtained with a balanced output. This is a sufficient value as a drive signal for an ECL logic circuit.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments and can be modified in various ways.

For example, impedance elements Z1, Z2
are assumed to be resistors of the same value, but these may be diodes connected in the forward direction with respect to the emitter current of the transistor. In this case, due to the forward voltage of the diode, the transistor connected to the cut-off transmission gate has a typical value of about 6
pA level and almost completely blocked.

As described above, in the present invention, the two transistors forming the differential circuit operate as a common base amplifier. Since impedance elements such as resistors and diodes are connected in series with the emitter, stray capacitances of these elements are also connected to the emitter. However, the emitter is approximately 2
Since the impedance is essentially low at 60Ω, and the emitter potential hardly changes depending on the signal level, these effects can be ignored.

Furthermore, from the perspective of the CMOS logic circuit, whereas the conventional example drives a high-resistance attenuation circuit and stray capacitance as loads, the present invention only drives the gates of two MOS transistors. Therefore, there is no delay due to the attenuation circuit.

For example, with a stray capacitance of about 1 pF as in the conventional example, the delay is about 0.26 nS, which can be said to be a significant improvement.

[0037]

[Effects of the Invention] As explained above, the amplitude conversion circuit of the present invention is achieved by short-circuiting the impedance element inserted into the essentially low-impedance emitter terminal of the transistor constituting the differential circuit using an analog switch. ,
This has the effect of reducing the delay caused by stray capacitance to a negligible extent, and therefore speeding up the operation of the circuit without increasing current consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of an amplitude conversion circuit of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional amplitude conversion circuit.

FIG. 3 is a circuit diagram showing an equivalent circuit of the attenuation circuit shown in FIG. 2;

[Explanation of symbols]

1 Differential circuit 2, 3 Transmission gate 4, 5
Inverter circuit 6 CMOS logic circuit 7 Attenuation circuit 8 Bias circuits N1 to N4 N-channel MOS transistor P
1 to P4 P-channel MOS transistor Q1
,Q2 Transistor R1~R7 Resistor

Claims (4)

[Claims] 1. First and second transistors forming a differential circuit and outputting correction and correction output signals, a constant current source supplying an operating current of the differential circuit, the constant current source and the Complementary first and second analog switch circuits are connected between respective emitters of the first and second transistors, and have impedance elements connected in parallel. 1. An amplitude conversion circuit comprising: a switch control circuit that controls the conduction state or the cutoff state. 2. The analog switch circuit connects the respective drains and sources of the P-channel MOS transistor and the N-channel MOS transistor in common, and controls the respective gates to be in the conduction state or the cutoff state by pulses of complementary polarity. 2. The amplitude conversion circuit according to claim 1, wherein the amplitude conversion circuit is a transmission gate circuit. 3. The amplitude conversion circuit according to claim 1, wherein the impedance element is a resistance having a sufficiently larger value than the conduction resistance of the analog switch circuit. 4. The amplitude conversion circuit according to claim 1, wherein the impedance element is a diode connected in a forward direction with respect to a current flowing from the emitter to the constant current source.