JPH0425946A - Circuit self-diagnostic system - Google Patents

Abstract

PURPOSE:To obtain a circuit self-diagnostic system in which the margin of circuit parts as against the fluctuation of a power voltage in addition to the fluctuation of an operation clock frequency by conducting a test while a basic operation clock frequency is fluctuated. CONSTITUTION:A basic operation clock generation circuit 1 is set to be a crystal oscillation type, for example. Thus, a highly precise basic operation clock signal is generated. The basic operation clock signal is usually supplied to respective parts of the device with an operation clock through a selector 4. On the other hand, the basic operation clock signal is supplied to a PLL circuit 3. A clock signal with the frequency fluctuation width of about + or -10% degrees is separately generated as against the basic operation clock frequency and it is supplied to respective parts of the device through the selector 4 at the time of an intra-device clock margin test. Thus, the circuit parts with a small allowance degree as against the operation clock frequency fluctuation can be detected in an early stage.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a circuit self-diagnosis method for data processing bags and equipment in general, and in particular, the basic operation clock frequency is varied and the basic operation is performed in parallel. The present invention relates to a circuit self-diagnosis method that tests the operation of internal circuits while varying the power supply voltage.

[Conventional technology]

Various electronic devices, including data processing devices, are composed of various circuit components, and early detection of deterioration and defects in these circuit components is important when considering the daily operating rate of these devices. The following items are listed as one of the important items.

Note that Japanese Patent Application Laid-open No. 146135/1983 is cited as a technique for early detection of deterioration and defects in circuit components.

[Problem to be Solved by the Invention] However, in the case of the above publication, even circuit components that are in the process of deterioration are detected by varying the power supply voltage, but this test is limited to the power supply voltage. It is concerned with the margin of circuit components against fluctuations in , and nothing more. Generally, the operation of circuit components depends largely on the voltage of the power supply, but changes in the operating clock frequency can also cause
Its operation may be greatly affected.

An object of the present invention is to provide a circuit self-diagnosis method that takes into consideration the margin characteristics of circuit components with respect to fluctuations in operating clock frequency.

Another object of the present invention is to provide a circuit self-diagnosis method that takes into consideration the margin of circuit components against fluctuations in power supply voltage in addition to fluctuations in operating clock frequency.

[Means for Solving the Problem] The above object is achieved by conducting a test while varying the basic operating clock frequency.

Further, another object is achieved by conducting a test while simultaneously varying both the basic operating clock frequency and the basic operating power supply voltage.

[Effect]

The basic operating clock frequency is varied within a certain range, and it is tested whether the circuit components can respond correctly to this variation. If the basic operating power supply voltage is also varied in parallel with the variation, the operation of each circuit component will be more severely tested.

〔Example] The present invention will be explained below with reference to FIGS. 1 and 2.

First, the clock generating section as a main part of the data processing apparatus according to the present invention will be explained. FIG. 1 shows the configuration of an example thereof. As shown in the figure, the basic operation clock generation circuit 1 is of a crystal oscillation type, for example.
Therefore, a highly accurate basic operation clock signal is generated. Under normal conditions, this basic operating clock signal is supplied to various parts within the device via the selector 4 as an operating clock. On the other hand, the basic operation clock signal is supplied to the PLL circuit 3, and the PLL circuit 3
For example, ±10% of the basic operating clock frequency.
A clock signal having a frequency fluctuation range of approximately 100% is separately created, and is supplied to each part within the device via the selector 4 during an internal clock margin test.

Specifically, the PLL circuit 3 includes a frequency divider that programmably divides the basic operating clock signal (the divided output becomes one input to the phase comparator), and a voltage-controlled optical oscillator (VCO).
) A frequency divider that divides the output in a programmable manner (the divided output serves as another input to the phase comparator). If the frequency division ratios of these frequency dividers are automatically and sequentially programmably controlled by the frequency setting circuit 2, the clock signal whose frequency is sequentially varied within a preset frequency variation width is transmitted to the PLL circuit 2.
It is more easily obtained.

FIG. 2 shows the configuration of the clock generating section in another example. As shown in the figure, the basic operating clock signal is generated in the same manner as in Figure 1 and is supplied to each part within the device, but its frequency is varied sequentially within a preset frequency variation range. The clock signal is generated independently of the basic operation clock signal. Control voltage command values are sequentially generated from the voltage setting circuit 5, and by acting on the voltage-controlled optical oscillator 7 as an analog control voltage via the D/A converter 6, a frequency corresponding to the control voltage is set. A clock signal is obtained from the voltage-controlled optical oscillator 7.

As described above, it is possible to perform an internal clock margin test, but in order to perform an internal voltage margin test at the same time, it is sufficient to configure the power supply section as a programmable power supply. . Under normal conditions, the basic operating power supply voltage is supplied to each part of the device as the operating voltage, but during voltage margin tests, the operating voltage is changed sequentially within a preset voltage fluctuation range. All you have to do is make sure you can get it.

[Effects of the Invention] As described above, according to claim 1, circuit components with a small margin for operating clock frequency fluctuations can be detected at an early stage, and according to claim 2, the operating clock frequency,
This means that circuit components with little margin for fluctuations in operating power supply voltage can be detected at an early stage.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are diagrams each showing a configuration example of a Cronk ordering section according to the present invention. DESCRIPTION OF SYMBOLS 1... Basic operation clock generation circuit, 2... Frequency setting circuit, 3... PLL circuit, 4... Selector, 5...
... Voltage setting circuit, 6... D/A converter, 7... Voltage controlled oscillator. Patent applicant Hitachi Communication Systems Co., Ltd. Agent Patent attorney Masami Akimoto (1 other person) Fig.

Claims (1)

[Claims] 1. A circuit self-diagnosis method for a data processing device equipped with a self-diagnosis function, which uses the basic operating clock during an initial test at power-on startup or an operation test during maintenance and inspection. A circuit self-diagnosis method that performs tests while varying the frequency within a certain range around the frequency. 2. The circuit self-diagnosis system according to claim 1, wherein the basic operating power supply voltage is varied within a certain range around the voltage in parallel with the variation of the basic operating clock frequency.