JPH04259986A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To automatically set the cycle of a memory holding operation corresponding to fluctuation in the data holding ability of a memory cell with the fluctuation of an outside power source concerning a cycle setting circuit to set the cycle of the memory holding operation required for a DRAM. CONSTITUTION:A ring oscillator power source Vosc to be fluctuated reversely to the voltage fluctuation of an outside power source Vcc or a ring oscillator power source Vosc to be fixed regardless of the voltage fluctuation of the outside power source Vcc is supplied from a power supply circuit 5 to a ring oscillator 2 and the memory holding operation is executed to the memory cell in the cycle based on the oscillation frequency of the ring oscillator 2 to be oscillated by the ring oscillator power source Vosc.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cycle setting circuit for setting the cycle of memory retention operations necessary for a DRAM. Recent DRAMs are equipped with a self-refresh mode in which the cycle of memory retention operation is set by an internal circuit without requiring an external clock signal. In this self-refresh mode, the period of memory retention operation is constant regardless of the power supply voltage or ambient temperature, etc.
Alternatively, if the data retention capacity of the memory cell is high, that is, the power supply voltage is high, the cycle of the memory retention operation is lengthened, and if the data retention capacity of the memory cell is low, that is, the power supply voltage is low, the cycle of the memory retention operation is lengthened. needs to be shortened.

0002

2. Description of the Related Art A cycle setting circuit for a memory retention operation in a conventional DRAM with a self-refresh mode will be explained with reference to FIG. V
The ring oscillator 2 oscillates at a predetermined frequency based on the supply of cc, and the output signal of the ring oscillator 2 is output to, for example, an n-bit counter 3. The counter 3 counts the pulse signals output from the ring oscillator 2, and when a predetermined number of pulse signals are counted, outputs an operation control signal ΦR for performing a memory retention operation, and outputs the operation control signal ΦR.
Data stored in a large number of memory cells is sequentially refreshed based on the data.

0003

[Problems to be Solved by the Invention] In the above-described period setting circuit, the oscillation frequency changes based on the voltage fluctuation of the external power supply Vcc, and as shown in FIG. 7, when the power supply voltage increases, the oscillation frequency changes. increases, and if it decreases, the oscillation frequency decreases. As a result, when the voltage of the external power supply Vcc increases, the cycle of the memory retention operation becomes shorter, and when the voltage of the external power supply Vcc decreases, the cycle of the memory retention operation becomes longer.

On the other hand, when data is written to each memory cell while the external power supply Vcc is high, the data retention capacity of each memory cell improves, so the period of the memory retention operation may be long, and when the external power supply Vcc is low, When data is written into each memory cell, the data retention capacity of each memory cell decreases, so it is necessary to shorten the period of memory retention operation.

Therefore, in the above-described cycle setting circuit, it is necessary to reduce the power supply voltage of the external power supply Vcc and shorten the cycle of the memory retention operation with respect to the cycle of the memory retention operation set with a specific external power supply voltage. On the contrary, sometimes the cycle becomes longer, and when the power supply voltage of the external power supply Vcc increases and the cycle of the memory retention operation can be long, there is a problem that the cycle becomes shorter.

An object of the present invention is to provide a semiconductor memory device equipped with a cycle setting circuit that can automatically set the cycle of memory retention operation in response to variations in the data retention capacity of memory cells due to variations in external power supply. There is a particular thing.

[0007]

[Means for Solving the Problems] FIG. 1 is an explanatory diagram of the principles of the first and third inventions. That is, in the first invention, the ring oscillator power supply Vosc, which fluctuates in the opposite direction to the voltage fluctuation of the external power supply Vcc, is supplied from the power supply circuit 5 to the ring oscillator 2, and the ring oscillator power supply Vosc is supplied from the power supply circuit 5 to the ring oscillator 2.
A memory holding operation is performed on the memory cell at a period based on the oscillation frequency of the ring oscillator 2 oscillated by c.

Further, in the second invention shown in FIG. 2, a reference voltage VF that fluctuates with fluctuations in the external power supply Vcc is input to the gates of a plurality of transistors Tr1 to Tr4 having different threshold values, and the reference voltage VF The transistors Tr1 to Tr sequentially turn on and off as the
By changing the combined resistance value of the resistors R7 to R11 connected in parallel between the external power source Vcc and the ring oscillator 2 based on the operation of step 4, the voltage changes in the opposite direction to the voltage fluctuation of the external power source Vcc. A power supply circuit 5 that forms the ring oscillator power supply Vosc was constructed.

Further, in the third invention, the external power supply Vcc
A constant ring oscillator power supply Vosc is supplied from the power supply circuit 5 to the ring oscillator 2 regardless of voltage fluctuations, and memory is held in the memory cell at a period based on the oscillation frequency of the ring oscillator 2 oscillated by the ring oscillator power supply Vosc. perform an action.

0010

[Operation] In the first invention, when the voltage of the external power supply Vcc rises and the data retention capacity of the memory cell increases, the oscillation frequency of the ring oscillator 2 decreases and the period of the memory retention operation becomes longer. When the voltage decreases and the data retention ability of the memory cell decreases, the oscillation frequency of the ring oscillator 2 increases and the period of the memory retention operation becomes shorter.

Furthermore, in the third aspect of the invention, the oscillation frequency of the ring oscillator 2 remains constant regardless of fluctuations in the external power supply Vcc, and the period of the memory holding operation remains constant.

0012

[Example] An example embodying this invention is shown below in Figure 2.
and will be explained according to FIG. Incidentally, the same components as those of the conventional example are given the same reference numerals, and the explanation thereof will be omitted. As shown in FIG. 2, the period setting circuit of this embodiment has, for example, four N
The drains of the channel MOS transistors Tr1 to Tr4 are supplied with an external power supply Vcc via resistors R1 to R4, respectively, and the sources are connected to ground G. And threshold value Vth1 of each transistor Tr1 to Tr4
~Vth4 is Vth1 <Vth2 <Vth3
The relationship is set to be <Vth4.

The gates of each of the transistors Tr1 to Tr4 are supplied with an external power supply Vcc via a resistor R5 and are connected to ground G via a resistor R6. Therefore, a reference voltage VF obtained by dividing the external power supply Vcc by resistors R5 and R6 is input to the gates of the transistors Tr1 to Tr4. The drains of each transistor Tr1 to Tr4 are connected to the gates of P channel MOS transistors Tr5 to Tr8 via an inverter circuit 4, respectively, and each transistor T
The external power supply Vcc is supplied to the sources of r5 to Tr8 through resistors R7 to R10, respectively, and the drains are connected to the power supply terminals of each inverter circuit 1 constituting the ring oscillator 2 to supply the ring oscillator power supply Vosc. . In addition, transistors Tr5 to Tr8 and resistor R7
A resistor R11 is connected in parallel to ~R10. Then, the output signal of the ring oscillator 2 is transmitted to the counter 3.
It is output to .

Now, in the above configuration, the external power supply Vc
The reference voltage VF based on c is applied to each transistor Tr1 to T
When it is lower than the threshold value Vth1 to Vth4 of r4, each transistor Tr1 to Tr4 is turned off and the inverter circuit 4 outputs an L level signal.
r5 to Tr8 are turned on. Therefore, resistors R7 to R11
The external power supply V is applied to ring oscillator 2 based on the combined resistance of
A ring oscillator power supply Vosc having a voltage lower than cc is supplied.

On the other hand, as shown in FIG. 3, as the voltage of the external power supply Vcc increases, the reference voltage VF increases and the threshold voltages Vth1 to Vth of the transistors Tr1 to Tr4 increase.
4, each of the transistors Tr1 to Tr4 is sequentially turned on as the reference voltage VF rises, and accordingly, the transistors Tr5 to Tr8 are sequentially turned off, and the connection between the resistors R7 to R10 and the ring oscillator 2 is sequentially disconnected. Therefore, the combined resistance of the resistors R7 to R11 increases sequentially. As a result, the ring oscillator power supply Vosc decreases as the voltage of the external power supply Vcc increases, so that the oscillation frequency of the ring oscillator 2 decreases.

Therefore, in this period setting circuit, the external power supply V
The reference voltage VF is set to the transistor T based on the variation of cc.
When the threshold values of r1 to Tr4 vary within a range including Vth1 to Vth4, the oscillation frequency of the ring oscillator 2 decreases in four steps as the voltage of the external power supply Vcc increases, and the cycle for memory retention operation changes in four steps. On the other hand, as the voltage of the external power supply Vcc decreases, the oscillation frequency of the ring oscillator 2 increases in four steps, and the period for memory retention operation can be shortened in four steps. As a result, it is possible to automatically set a memory retention operation cycle that always matches the data retention capacity of the memory cell.

Next, a second embodiment embodying the present invention will be described with reference to FIG. In this embodiment, the external power supply Vcc
is made into a constant voltage by a constant voltage power supply circuit 5 and supplied to the ring oscillator 2 as a ring oscillator power supply Vosc, and the constant voltage power supply circuit 5 is constituted by a known constant voltage circuit. With this configuration, as shown in FIG. 5, even if the voltage of the external power supply Vcc increases, the ring oscillator power supply Vo
Since sc is constant, the period of the memory retention operation can be kept constant.

[0018]

As described in detail above, the present invention provides a semiconductor memory device that can automatically set the period of memory retention operation in response to variations in the data retention capacity of memory cells due to variations in the voltage of an external power supply. It can exhibit excellent effects.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a characteristic diagram showing the operating characteristics of the first embodiment.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a characteristic diagram showing the operating characteristics of the second embodiment.

FIG. 6 is a circuit diagram showing a conventional example.

FIG. 7 is a characteristic diagram showing the operating characteristics of a conventional example.

[Explanation of symbols]

2 Ring oscillator 5 Power supply circuit Vcc External power supply Vosc ring oscillator power supply VF Reference voltage Tr1~Tr4 Transistor R7~R11 Resistance

Claims (3)

[Claims] Claim 1: A semiconductor memory device that performs a memory retention operation on a memory cell at a period based on the oscillation frequency of a ring oscillator (2) that oscillates when power is supplied, the semiconductor memory device being capable of retaining memory in response to voltage fluctuations in an external power supply (Vcc). On the other hand, the ring oscillator power supply (Vosc) which fluctuates in the opposite direction is
) to the ring oscillator (2). 2. The power supply circuit (5) inputs a reference voltage (VF) that fluctuates with fluctuations in the external power supply (Vcc) to the gates of a plurality of transistors (Tr1 to Tr4) having different threshold values; The transistor (
resistors (Tr1 to Tr4) connected in parallel between the external power supply (Vcc) and the ring oscillator (2);
2. The semiconductor memory device according to claim 1, wherein the ring oscillator power supply (Vosc) fluctuates in a direction opposite to the voltage fluctuation of the external power supply (Vcc) by changing a combined resistance value of R7 to R11). 3. A semiconductor memory device that performs a memory retention operation on a memory cell at a period based on the oscillation frequency of the ring oscillator (2) that oscillates when power is supplied, wherein the voltage of the external power supply (Vcc) 2. The semiconductor memory device according to claim 1, wherein the ring oscillator power (Vosc), which is constant regardless of fluctuations, is supplied from a power supply circuit (5) to the ring oscillator (2).