JPH04264277A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make variable a pulse width of an incorporated pulse generating circuit, regarding a semiconductor integrated circuit having a gate array and a memory in one chip. CONSTITUTION:In a semiconductor integrated circuit having a gate array and a memory in one chip, a pulse generating circuit which outputs a write enable signal for writing data in a memory cell with the pulse width of the signal being switched between an ordinary mode and a test mode by a mode switching control signal from outside is provided in the memory. The pulse generating circuit is so constructed as to have a function of varying the pulse width in linkage with an external source voltage or a function of selecting the pulse width by using a delay circuit selecting terminal, in the test mode.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a gate array and a memory in one chip, and more particularly to an improvement in a built-in pulse generating circuit.

0002

2. Description of the Related Art FIG. 3 is an explanatory diagram of a conventional example. In the conventional pulse generation circuit, the circuit is shown in Fig. 3 (a) and the circuit shown in Fig. 3 (
As shown in the circuit diagram of the gates in b), in the delay circuit (Gate A group) that creates the pulse width, the power supply is GND-VEE1 (common to VEE2) or GND-VEE1 (common to VEE2).
There were ND-VEE1 and GND-VEE2, and the power supply voltage was fixed at a constant value.

0003

[Problem to be Solved by the Invention] Therefore, in conventional pulse generators, the pulse width is set by the number of gate stages. Therefore, if it becomes necessary to make the pulse width variable, the wafer process photomask must be revised and the circuit wiring pattern modified. There was a need.

[0004] For this reason, measurements cannot be made with the necessary pulse width, and the test conditions deviate from the appropriate values, causing problems in determining pass/fail in electrical characteristic tests of semiconductor integrated circuit devices. In view of the above points, the present invention is provided for the purpose of making the pulse width variable through circuit improvements without requiring any revision of the photomask.

[0005]

[Means for Solving the Problems] FIGS. 1 and 2 are diagrams explaining the principle of the present invention and explanatory diagrams of embodiments. In order to solve the above problem, as shown in Figure 1, the load drive current (
The power supply through which IEF) flows is separated, a new power supply with the power supply voltage VEE3 is provided, and by varying this power supply, IEF is changed, and as a result,
Either control the delay time of gate A group to vary the pulse width, or alternatively, as shown in Figure 2, provide several delay circuits for pulse generation, provide a terminal to select one of the delay circuits, and select the terminal. The pulse width can be arbitrarily selected according to the logic.

That is, an object of the present invention is to provide a semiconductor integrated circuit device having a gate array and a memory in one chip, to write data into a memory cell in response to an external mode switching control signal in the memory. It has a pulse generation circuit that switches the pulse width of the write enable signal between normal mode and test mode and outputs it. This can be achieved by having a function to vary the pulse width, or by having the pulse generation circuit have a function to select the pulse width using a delay circuit selection terminal during the test mode, as shown in Figure 2. Ru.

[0007]

[Operation] Compared to conventional power supplies, the present invention separates the load drive current of the gate that creates the pulse width and adds a delay circuit, making it possible to measure with the necessary pulse width. Ta.

[0008]

Embodiment FIG. 1 is an explanatory diagram of a first embodiment of the present invention. Regarding the first embodiment, first, the relationship between IEF and delay time will be described with reference to FIG.

In the previous circuit shown in FIG. 1(d), V
The current flowing through EE3 is IEF, the difference between VEE3 and the output (average of H/L) is ΔV, and the output and VEE3 are
Letting the resistance of R be R, it can be expressed by Equation 1.

0010

[Math 1]

Here, since the output and R do not depend on VEE3, IEE can be changed by changing VEE3.

Next, the relationship between IEF and delay time will be considered. Generally, as shown in FIG. 1(a), the delay time indicated by the time from input to output is expressed as: delay time = (delay time of gate A) + (delay time due to wiring capacitance).

Further, the relationship between the wiring capacitance (c) and the delay time due to the capacitance is shown in FIG. 1(b). As mentioned above, IE
By increasing F, the load driving ability increases,
As a result, the delay time becomes smaller.

Therefore, the delay time is different from the IEF shown in FIG. 1(d) in the gate A group shown in FIG. 1(c).
A new power supply is provided as an independent power supply VEE3. It is assumed that the B, C gates and others flow to VEE2.

[0015] By separating the power sources in this way,
The power supply voltage of VEE3 can be made variable,
IEF changes by varying the power supply voltage, and as a result, the delay time due to the gates of group A can be controlled.

In other words, the pulse width can be freely controlled by the power supply voltage. Next, a second embodiment will be explained with reference to FIG. 2.

In the conventional circuit shown in FIG. 2(a), there was only one delay circuit for pulse generation in gate group A, and the pulse width could not be changed, so this circuit was modified.
A new circuit shown in FIG. 2(b) is formed.

That is, as a new circuit, four delay circuits A, B, C, and D for pulse generation are provided, two terminals S1 and S2 are provided for selecting the delay circuits, and the logic of the terminals is The pulse width can be selected arbitrarily.

That is, the pulse width is made variable in a pseudo manner. Also, if you want to have more pulse width selectors, you can increase the number of logic terminals and delay circuits. For example, as shown in Figure 2(c), increasing the number of logic terminals means that the terminal is
, S2, four selections A, B, C, and D are possible, but with three terminals, the number increases further and eight selections are possible.

[0020]

[Effects of the Invention] As explained above, according to the present invention, by varying the pulse width, test conditions can be relaxed,
Characteristics can be judged with high precision, which greatly contributes to the improvement of testing technology.

[Brief explanation of the drawing]

[Fig. 1] Explanatory diagram of the first embodiment of the present invention

[Figure 2]
Explanatory diagram of the second embodiment of the present invention

[Figure 3] Explanatory diagram of conventional example

[Explanation of symbols]

IEF Load drive current VEE Power supply voltage C Wiring capacity S1, S2　　Delay circuit selection terminal

Claims (2)

[Claims] Claim 1: In a semiconductor integrated circuit device having a gate array and a memory in one chip, a pulse width of a write enable signal for writing data into a memory cell by an external mode switching control signal in the memory. A semiconductor, comprising: a pulse generation circuit that outputs a signal by switching it between a normal mode and a test mode; the pulse generation circuit has a function of varying the pulse width in conjunction with an external power supply voltage during the test mode; Integrated circuit device. 2. In a semiconductor integrated circuit device having a gate array and a memory in one chip, the pulse width of a write enable signal for writing data into a memory cell by an external mode switching control signal in the memory. A semiconductor, comprising: a pulse generation circuit that outputs a signal by switching it between a normal mode and a test mode; the pulse generation circuit has a function of selecting a pulse width using a delay circuit selection terminal in the test mode; Integrated circuit device.