JPH0426574B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] It is determined whether or not each line of asynchronous multiple lines is in a communication state at least once within the time of a communication data unit, for example, 1 bit, and the asynchronous multiple lines This made it possible to exchange data between the two.

[Industrial application field]

The present invention relates to an asynchronous line multiple processing system, and more specifically, the present invention relates to an asynchronous line multiple processing system, and more specifically, it is possible to exchange data between asynchronous lines by enabling communication data to be exchanged on all remaining lines while communication data is being exchanged on any line. This invention relates to an asynchronous line multiplexing method that performs.

In a data communication system, a data processing unit provided therein is connected not only to a single data line but also to a plurality of data lines. The successful operation of a data communications system including such data lines requires that the data processing unit be capable of multiplexing the data lines, whether or not they are synchronized. be.

[Conventional technology]

Functions such as flag sending and detection; zero insertion and deletion; CRC generation and inspection in the link control unit of the data link (for example, HDLC) of conventional data communication lines are provided in the hardware logic LSI, and the LSI typically supported a single channel.

[Problem that the invention seeks to solve]

If an attempt is made to control multiple lines using the above-mentioned LSI, it is necessary to prepare as many LSIs as there are lines, which is disadvantageous in terms of cost.

Therefore, although multiple processing methods that enable multiple processing of such multiple lines using a time-division method have been put into practical use, this method has the decisive disadvantage that it cannot be used unless the lines are synchronized. It has strong weaknesses.

The present invention was created in view of such problems, and an object of the present invention is to provide an asynchronous line multiple processing system that can perform multiple processing on a plurality of lines even if the lines are asynchronous.

[Means for solving the invention]

FIG. 1 shows a block diagram of the principle of the present invention. As shown in the figure, in order to multiplex processing of data from or to a plurality of asynchronous lines, the present invention allows each line of a plurality of asynchronous lines to be processed at least once within a communication data unit time of any line. The multiplex control unit 1 determines whether or not a communication state is established, thereby making it possible to send and receive data to and from these lines.Each line ₂₁ ... _2o has a communication request generation unit ₄₁ ... ...4 _o and a communication data holding section 5 ₁ ...5 _o . The multiplex control section includes a scanning section 6, _a scanning control section ₇ , and a communication processing section 8. It is configured by providing the following.

[Effect]

Regardless of whether or not a communication request is generated in the corresponding communication request generating section in any of the lines, the scanning section 6 scans at least one of the plurality of lines within the communication data unit time under the control of the scanning control section 7. Scan twice. The communication request generating section 4 ₁ ... of each line corresponding section 3 ₁ ... 3 _o that is scanned in this way
. . 4 _o and the communication data holding section 5 ₁ ... 5 _o are subjected to line recognition (identification) processing by the communication processing section 7.
In other words, the line handling units 3 ₁ ... 3 _o are sequentially connected to the communication processing unit 8 via the scanning unit 6 at predetermined time intervals.
is identified by a scan control signal (line identification information) from the scan control section 7.

Therefore, if a reception request is generated as a communication request, the communication data holding unit ₅₁ ...
...5 The received data unit given from _o via the scanning section 6 is sent to the communication processing section 8 according to the above-mentioned line identification information.
The sample is taken in and subjected to subsequent processing.
Furthermore, if a transmission request is generated as a communication request, the transmission data unit is transmitted from the communication processing section 8 via the scanning section 6 to the communication data holding section corresponding to the line identification information according to the above-mentioned line identification information, and is stored in the communication data holding section corresponding to the line identification information. transmitted to.

When such communication processing of communication data is performed on a communication data unit for a certain line,
The same applies to all other lines within the communication data unit time. This makes it possible to perform asynchronous multiplex processing on multiple lines.

It should be noted that in each communication in units of communication data as described above, the corresponding communication request generating section is reset each time to prepare for communication in the next unit of communication data.

〔Example〕

FIG. 2 shows an embodiment of the invention.

In this figure, 3R ₁ , ..., 3R _o are receiving line corresponding parts (corresponding to the receiving side of the line corresponding part in Figure 1) connected to the receiving lines 2R ₁ , ..., 2R _o , and these line corresponding parts Since they have the same configuration, the reception line corresponding section 3R _i is shown in FIG. 3 as a representative. As is clear from FIG. 3, the receiving line corresponding section 3R _i consists of a receiving data flip-flop 10 _i and a receiving request flip-flop 12 _i , which receive their clock input CLK as a receiving clock RC, and have a clear input CLR which will be described later. The reception response signal RAK _i sent from the multiplex control section 1 is received as shown in FIG. Reception data RD _i is supplied to the D input of the data flip-flop 10 _i , and its Q output is used as the reception data output. “1” in the D input of request flip-flop _12i
is supplied, and its Q output is the request signal RRQ _i
used as.

3T ₁ ,..., 3T _o is the transmission line 2T ₁ ,..., 2
This is the transmission line correspondence section connected to T _o (corresponding to the transmission side of the line correspondence section in Figure 1).Since these line correspondence sections have the same configuration, Figure 4 represents the transmission line correspondence section 3T _i . show. As shown in the figure, the line support section 3
T _i is a flip-flop for transmission data 20 _i , 22 _i
and a transmission request flip-flop _24i . The transmission clock TC is supplied to the clock input CLK of the transmission data flip-flops 22 _i and 24 _i , and the clock input CLK of the transmission data flip-flop (transmission buffer) 20 _i and the clear input of the transmission request flip-flop 24 _i
The CLR is supplied with a transmission response signal TAK _i sent from the multiplex control unit 1 as described later. As will be described later, the transmission data TD is supplied from the multiplex control section 1 to the D input of the transmission data flip-flop _20i , and its latch output Q is supplied to the D input of the transmission data flip-flop _22i . The output Q of the flip-flop 22 _i for transmission data is the transmission line 2.
Used for transmission to T _i .

Receive request RRQ _i and received data described above
Each of the RD _i (flip-flop outputs) is sent to the control circuit 36R (corresponding to the receiving side of the communication processing section 8 in FIG. 1) via the corresponding selectors 30R and 32R of the multiplex control section 1. This control circuit 36R is capable of data transfer to a processing section (not shown) via a bus interface 38. The reception response signal RAK _i generated from the control circuit 36R is supplied to the clear input CLR of the reception request flip-flop 12 _i of the corresponding line correspondence section 3R _i via the decoder 34R. In order to generate such a signal flow, selectors 30R, 32R, decoder 34R (corresponding to the receiving side of scanning section 6 in FIG. 1), control circuit 36R, and counter 40 (corresponding to scanning control section 7 in FIG. A control signal (count value) which corresponds to the above-mentioned line and is generated sequentially at predetermined time intervals is provided from the corresponding circuit (for details of its use, see the explanation regarding FIG. 5F below). This counter 40 is constructed in a ring format, and its one-round time is set so that it appears at least once within the time required for a communication data unit, for example, one bit, to be transmitted and received via any line.

A system that shares this counter and has the same functional configuration as the system on the receiving side is also provided on the transmitting side. That is, each of the transmission requests TRQ _i is sent to the control circuit 36T (corresponding to the transmission side of the communication processing section 8 in FIG. 1) via the selector 30T, and
The transmission data TD _i from T is supplied to the transmission data flip-flop 20 _i of the corresponding line corresponding section 3T _i via the decoder 32T. Also, the control circuit 3
The transmission response signal TAK _i generated from 6T is sent via the decoder 34T to the clear input CLR of the transmission data flip-flop _{20 i and} the transmission request flip-flop 24 _i of the corresponding line corresponding section 3T i.
supplied to Selector 30T that constitutes this system
and decoders 32T, 34T (scanning unit 6 in FIG.
The control circuit 36T also receives the count value of the counter 40 (corresponding to the transmitting side) and the control circuit 36T as well as the receiving side system (for details of its use, see the explanation regarding FIG. 6E below). Control circuit 34T is also enabled to receive data via bus interface 38.

Next, data transmission and reception operations under the above configuration will be explained. For convenience of explanation, data reception will be described first.

Since the asynchronous reception data of each line is also captured in the manner described below, line 2R _i
The reception mode will be explained by focusing on the following.

Receive clock RC (A in Figure 5) via line 2R _i
The reception request flip-flop 12 _i of the line corresponding section 3R _i which receives the data (see D and B) is set, and the reception request RRQ _i is generated therefrom (see D in FIG. 5). At the same time, the received data RD
is set in the receive data flip-flop responsive to the receive clock RC (see FIG. 5C).

An operation similar to the operation of this line correspondence section 3R _i is asynchronously caused in other line correspondence sections.

Each line data thus set in the line corresponding _sections 3R ₁ , .

As described above, these selectors 30R and 32R are caused to perform the following selection operation (scanning operation) by the counter 40. That is, as shown in F in FIG. 5, during the reception time (so-called communication data unit time in FIG. 1) given to the received data on line 2R _i , for example RD ₀ , the own reception request is
The selectors 30R and 32R not only detect RRQ _i , take in the received data RD _i , and send the reception response RAK, but also perform the same process at least once for all other lines.
The inputs to the control circuit 36R are sequentially connected to the control circuit 36R via these selectors, and the control circuit 36R causes the control circuit 36R to perform reception processing in response to the input information and the count value from the counter 40. , and a reception response signal RAK is returned to the necessary line corresponding section via the decoder 34R.

By doing this, the received data of any line will be at least once within the received data unit time.
You will be given an opportunity to incorporate the times. In other words, failures due to line asynchrony do not occur in the receiving data acquisition process in the multiplex control unit 1, and a smooth flow of data from the lines 2R ₁ , . . . , 2R _o to the control circuit 36R occurs. be able to.

In the same way, transmission data is sent out to an asynchronous transmission line.

That is, as shown in E of FIG. 6, during the transmission time (communication data unit time according to the configuration of FIG. 1) given to the transmission data TD _i to the line 2T _i , the self-transmission request TRQ _i is detected and The input to the selector 30T (transmission request: D in FIG. 6) is set so that not only the transmission data TD _i and the transmission response TAK _i are sent, but also the same process is performed at least once for all other lines. The input information, the transmitted data and the counter 40 are sequentially connected to the control circuit 36T via the selector 30T.
By causing the control circuit 36T to perform a transmission process in response to the count value from the control circuit 36T, the transmission data from the control circuit 36T is transmitted to the corresponding line corresponding section 3T _i via the decoder 32T. At the same time, the transmission response signal _{TAK i} is sent to the data flip-flop _{20 i and} the transmission request flip-flop 24 _i via the decoder 34T _i . As a result, the transmission data flip-flop (transmission buffer) 2
The transmission data is set to 0 _i (see C in FIG. 6), and the transmission data is set in the transmission flip-flop 22 _i by the next transmission clock TC (see B in FIG. 6). That is, it is transmitted to the transmission line 2T _i (see A in FIG. 6). In addition, the flip-flop _24i for transmission requests is the transmission clock TC.
is set by TRQ to generate a transmission request TRQ _i .

By doing this, the transmission data to any line will be given at least one opportunity to be transmitted within the transmission data unit time. In this way, even if a plurality of lines are asynchronous, the transmission data can be successfully transmitted from the multiplexing unit 1 to these lines.

In the above embodiment, an example in which the communication data unit time is 1 bit time has been explained in order to facilitate understanding of the present invention, but the present invention is not limited to this. Accordingly, it is necessary to make changes to the configuration of the line corresponding section and the delivery system between the line corresponding section and the above-mentioned control circuit, but this is not essential to the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, asynchronous line multiplexing processing becomes possible. Since the multiprocessing is performed in an integrated manner rather than individually, the required amount of hardware can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a block diagram of a receiving line corresponding section, and FIG. 4 is a block diagram of a transmitting line corresponding section.
Figure 5 is a diagram showing the reception timing chart, Figure 6 is a diagram showing the reception timing chart.
The figure is a diagram showing a transmission timing chart. In Fig. 1, 1 is a multiplex control unit, 2 ₁ ...2 _o
is the line, 3 ₁ ... 3 _o is the line support section, 4 ₁ ... 4 _o communication request generation section, 5 ₁ ... 5 _o communication data holding section, 6 is the scanning section, 7 is the scanning control section, 8 is communication This is the processing section.

Claims (1)

[Scope of Claims] 1. The communication data unit of any line appears at least once between the communication data units of each line, and the receive clock and receive data are transmitted asynchronously to each other when receiving from the opposing device. , when transmitting, there are multiple lines 2 that transmit the transmitting clock.
₁ ,...2 _o In a communication system equipped with a multiplex control unit 1 that performs data communication, a reception request or a transmission request is generated in response to the reception clock or transmission clock at the start of communication in units of communication data. The communication request generating unit 4 ₁ , . . . is reset at the end of the communication.
4 _o , and a communication data holding unit 5 ₁ , . . . which holds communication data during the communication time for each communication data unit.
5 _o and a line corresponding section for each line 3 ₁ ,...3 _o
The multiplex control unit 1 connected _to each _of the line corresponding units 3 ₁ , . A scanning unit 6 that takes in communication data from or sets communication data from the communication request generating unit ₄₁ ,...4o, and resets the communication request generating unit 41,... _{4o ,} and a communication time for a unit of communication data. a scan control section 7 that causes the scanning section 6 to perform at least one scan of a line corresponding section corresponding to a plurality of lines; 2 ₁ , ... 2 _o Recognition that the line corresponding section corresponding to any line is being scanned, and reception requests or transmissions input from the scanning section 6 during the scanning period of the recognized line corresponding section a process of fetching communication data held in a communication data holding unit of the recognized line corresponding unit in response to the request or a process of sending communication data to the communication data holding unit of the recognized line corresponding unit; An asynchronous line multiplexing system characterized in that a communication processing unit 8 performs a reset process to a communication request generating unit of a recognized line corresponding unit via a scanning unit 6.