JPH0426716B2 - - Google Patents

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention provides a method for measuring time by enlarging a fraction of the clock period when measuring clock signals. The present invention relates to an applied time measuring device.

(Prior art) As this type of time measuring device, the applicant has developed a third
We also proposed what is shown in the figure. In the figure, 101 is a signal input terminal to be measured, 102 is a timing signal forming circuit, 103 is an oscillator, 104 is a first flip-flop, 105 is a triangular wave forming means, 106 is an AND gate, 107 is a counting means, and 108a is a first sample and hold circuit. , 108b is a second sample and hold circuit, 109a is a second flip-flop,
109b is the third flip-flop; 110a is the third flip-flop;
1A/D (analog/digital) conversion means, 110
b is the second A/D conversion means, 111 is the calculation means, 1
12 is a display, 201 is a signal to be measured, 202 is a reset signal, 203 is a first timing signal, 20
4 is a second timing signal, 205 is a first clock signal, 206 is a second clock signal, 207 is a triangular wave, 208 is a counting clock signal, and 209a is a first clock signal.
Hold voltage 209b is second hold voltage 2
10a is a first discrimination signal, and 210b is a second discrimination signal.

In this operation, the oscillator 103 always outputs the first clock signal 205 having the period Te shown in FIG. 4E. This signal is frequency-divided by the first flip-flop 104 to produce a second clock signal 206 as shown in FIG. 4F.
get. Further, from this signal, a triangular wave forming circuit 105 at the next stage generates a triangular wave 207 having a peak-to-peak voltage of V ₀ as shown in FIG. 4G. The reset signal 20 of FIG. 4B is applied to the timing signal forming circuit 102.
2, when the signal under test 201 with the time interval Tx in FIG. 4A is first input to the input terminal 101, the first timing signal 203 in FIG. A second timing signal 204 shown in FIG. 4D indicating the falling edge of the timing signal 204 is outputted. First, the first timing signal 203
When is output, the voltage V ₁ of FIG. 4G, which is the voltage of the triangular wave 207 at that time, is held as the first hold voltage 209a of FIG. 4G in the first sample and hold circuit 108a. Further, the polarity of the slope of the triangular wave 207 at this time is detected by the second flip-flop 109a as the first discrimination signal 210a shown in FIG. 4, which is necessary as a calculation condition.

Apart from this, the time interval Tx of the signal under test 201
The gate 106 is opened during this period, the first clock signal 205 with a period T ₀ is passed, and a proportional number of pulses n
We obtain the counting clock 208 of FIG. 4H having a value of 1. Furthermore, the voltage V ₂ of FIG. 4G, which is the voltage of the triangular wave 207 at the time when the second timing signal 204 indicating the end of the time interval Tx of the signal under test 201 is output, is applied to the second sample and hold circuit 108b.
It is held as the second hold voltage 209b in FIG. 4G. In addition, the polarity of the slope of the triangular wave 207 at this time is determined by the second discrimination signal 2 of FIG.
10b. Next, the counting clock 208
is counted by the counting means 107. Further, the first hold voltage 209a is converted into a numerical value by the first A/D conversion means 110a, and the second hold voltage 209b is converted into a numerical value by the first A/D conversion means 110a.
The 2A/D conversion means 110b converts the data into numerical values, weights each value, and performs an addition operation in the calculation means 111. The results are displayed on display 112.

Here, when the polarity of the slope of the triangular wave is negative, the output of the second flip-flop is H logic, and similarly the third flip-flop output is H logic.
The output of the flip-flop is also H logic, and when the polarity of the slope of the triangular wave is positive, the outputs of the second and third flip-flops are L logic, and the outputs of the two flip-flops are expressed as P ₁ and P ₂ respectively, which is H logic. It is set to "0" when it is, and it is set to "1" when it is L logic.
Also, the time from the rising edge of the signal under test 201 to the first clock signal 205 that comes first is Δt ₁ ,
The time from the falling edge to the first clock signal 205 that was just before is Δt ₂ , the value obtained from the counting means 107 is n1, and the first A/D converting means 110
The value obtained from a is n2, and the second A/D conversion means 1
The value obtained from 10b is n3, 1st, 2nd A/D
When the full scale of the conversion means is n4 (this value and the voltage _V0 between the peaks of the triangular wave are equivalent),
The desired time interval Tx of the signal under test is Tx=T ₀ ×(n1-1)+Δt ₁ +Δt ₂ =T ₀ ×(n1-1)+(T ₀ /n4)×｜n4×P ₁ −n2｜+( It is obtained by T ₀ /n4)× |n4×P ₂ −n3|. In the above TX formula, (n1-1) and △
The digital values obtained for t1 and △t2 have different meanings, but if the meanings of these sizes are different, the above TX formula cannot be calculated, so the meaning of the addend term on which this calculation is performed The process of matching the sizes of the objects is called "weighting." Here, T0 and each T0/n4 of the three addend terms in the TX equation are "weights" used for the above-mentioned weighting. Further, P1 and P2 indicate the polarity of the slope of the triangular wave at both ends of TX.

However, in this case, the fractional times Δt ₁ , Δt ₂
The linearity _of the triangular wave, which is used as a means of determining The disadvantage is that it is extremely difficult.

(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and uses a triangular wave to measure time intervals shorter than the period of the clock signal used for measurement with higher precision than conventional methods. The aim is to provide a time measuring device that can

[Structure of the invention]

(Means and operations for solving the problems) The present invention provides a first means for outputting a signal indicating the starting edge and a signal indicating the ending edge of a time interval to be measured, and a reference clock signal having a certain period. a second means for generating a clock signal, a third means for obtaining a first clock signal having a known period from the reference clock signal, and a second clock signal having a phase shift therefrom; a fourth means for obtaining triangular waves synchronized with each other from a clock signal; a fifth means for holding respective voltages of each triangular wave at the beginning and end of the time interval to be measured; a sixth means for converting into digital values only those of the held voltage that fall within the linear slope of the triangular wave; and a sixth means for counting signals having a known period during the time interval to be measured. 7, and an eighth means for adding the value obtained by the means and the value converted into the digital value by giving necessary weights to each, and synchronizing with the clock signal. By using a pair of triangular waves with different phases, it is possible to always use the voltage near the middle of the voltage where the triangular wave has good linearity, making it possible to perform high-resolution and high-precision measurements without sacrificing high-speed measurement time. It is something.

(Example) An example of the present invention will be described below with reference to the drawings. Although FIG. 1 is a block diagram of the same embodiment, parts corresponding to those in FIG. 3 are given the same reference numerals and their explanation will be omitted. In FIG. 1, 301 is an oscillator, 302 to 305 are first to fourth flip-flops, 306a to 306b are first and second triangular wave shaping circuits, 307a to 307b are third and fourth sample and hold circuits, 308a to 308d is the first ~
The fourth switch, 309 is the fifth flip-flop,
310 is a counting clock forming means, 311 to 314
are the 1st to 4th gates, and 315 to 322 are the 6th to 4th gates.
13 flip-flops, 323 to 326 are fifth to eighth gates, 401 is a reference clock signal, 402 to
404 are third to fifth clock signals, 405a to 4;
05b is the first and second triangular wave, 406a, 406b
are the third and fourth hold voltages, 407 is the sixth clock signal, 408 to 411 are the first to fourth gate signals, and 412 to 419 are the first to eighth discrimination signals.

Oscillator 301 always outputs reference clock signal 401 shown in FIG. 2A. The reference clock signal 401 is frequency-divided by the first flip-flop 302 to the fifth flip-flop 309. Second clock signal 2 obtained from third flip-flop 304
06 to the first triangular wave forming circuit 306a.
A triangular wave 405a is output, and a second triangular wave 405b is output by a second triangular wave forming circuit 306b using the fifth clock signal 404 obtained from the fourth flip-flop 305.

A timing signal forming circuit 102 that outputs a first timing signal 203 indicating the rising edge of the signal under test 201 and a second timing signal 204 indicating the falling edge thereof, and a fourth clock signal 40
3, a counting clock forming means 310 that generates the first clock signal 205 from the clock signal 201, a gate 106 that passes the first clock signal 205 during the time interval Tx of the signal under test 201, and a counting clock signal 20 obtained therefrom.
Counting means 107 for counting 8, first to fourth gates 311 to 314 for detecting the polarity of the slope of the triangular wave at the time when the first timing signal 203 or the second timing signal 204 is generated, which one of the two triangular waves 6th to 13th to determine whether to use and the polarity of the slope of the triangular wave at that time.
Flip-flops 315 to 322, a first sample and hold circuit 108a that holds the voltage of the first triangular wave at the first timing 203, a third sample and hold circuit 307a that holds the voltage of the second triangular wave 405b at that time, and a second sample and hold circuit 307a that holds the voltage of the second triangular wave 405b at that time. A second sample and hold circuit 108b holds the voltage 209b of the first triangular wave 405a at the time of the timing signal 204, and a voltage 4 of the second triangular wave 405b.
06b, the two voltages held by the first timing signal 203, and the first and second circuits that pass either the first hold voltage 209a or the third hold voltage 406a, whichever is necessary for measurement. switch 308a, 308
b, the fifth and sixth gates 323 and 324 that generate the signals that control them, and the voltage between the two held by the second timing signal 204, and the second hold voltage 209b is the fourth hold voltage 406b.
3rd and 4th switches 308c and 308d that pass whichever is necessary for measurement, and 7th and 8th gates 325 and 32 that generate signals to control them.
6. Changing either the first hold voltage 209a or the third hold voltage 406a to a digital value
1A/D conversion means 110a, second hold voltage 2
09b or the fourth hold voltage 406b into a digital value, a second A/D conversion means 110b,
The values obtained from these two A/D conversion means and the first
~Eighth discrimination signals 412 to 419, counting means 107
A calculation means 111 for calculating the time interval Tx of the signal under measurement 201 from the value obtained from the calculation means 111 and a display 112 for displaying the result are provided.

In the operation shown in FIG. 1, the oscillator 301 always outputs the second
A reference clock signal 401 in FIG. A is output. This reference clock signal 401 is input to the first flip-flop 302, and the third clock signal 402 shown in FIG.
3 takes this as input and outputs the fourth clock signal 403 of FIG. 2C, and the third flip-flop 304 takes it as input and outputs the second clock signal 2 of FIG. 2D.
The fourth flip-flop 305, which receives the clock signal 06 as an input, obtains the fifth clock signal 404 in FIG. 2E, which is delayed in phase by 90 degrees. Furthermore, a second clock signal 206 synchronized with the second clock signal 206
The first triangular wave 405a with a peak-to-peak value of _v0 in FIG.
The second triangular wave forming circuit 306b outputs a second triangular wave 405b having a peak-to-peak value of _v0 in FIG.

Also, the phase is different when viewed from the fourth clock signal 403.
6th clock signal 40 of FIG. 2 N delayed by 90°
7 is obtained from the fifth flip-flop 309 using the third clock signal 402 and the fourth clock signal 403. From the first gate 311, the first gate shown in _FIG . The signal 408 is output from the second gate 312 at T ₀ /4 at a time when the positive slope of the first triangular wave 405a has good linearity, and into the pulse train P in FIG. The second gate signal ₄₀₉ shown in FIG. The third gate signal 410 in Fig. 2Q is formed from the fourth gate 314 by a pulse train centered at the middle of the slope at T ₀ /4, which is the time when the positive slope of the second triangular wave 405b has good linearity. 4 gate signals 411 shown in FIG. 2R are obtained.

Here, after the reset signal 202 shown in FIG. 2G is input to the timing signal forming circuit 102, when the signal under test 201 with the time interval Tx shown in FIG. 2F is input from the input terminal 101, the signal under test 201 is A first timing signal 203 in FIG. 2H indicating the beginning of the time interval Tx is output. The second timing signal 204 of FIG. 2I also indicates the end edge.
is also output. In the counting clock forming means 310, the first clock signal in FIG.
By obtaining the clock signal 205, passing the first clock signal 205 through the gate 106 during the time interval Tx of the signal under test 201, obtaining the counting clock signal 208 in FIG. 2M, and counting by the counting means 107, The basic time length of the time interval Tx can be determined as T ₀ (n1-1), where n1 is the count value. As the time that was not determined at this time, the fractional time of Δt ₁ and Δt ₂ in FIG. 2L remains as a residual value. These can be determined by the method shown below.

First, for the fractional time Δt ₁ , when the first timing signal 203 is output, the first sample and hold circuit 108a outputs the first triangular wave 405a at that time.
The voltage v ₁ of the second triangular wave 405b is held as the first hold voltage 209a, and the third sample hold circuit 307a holds the voltage v ₂ of the second triangular wave 405b as the third hold voltage 209a.
It is held as a hold voltage 406a. The first switch 308a and the _second switch 308a select a voltage corresponding to the intermediate T ₀ /4, whichever has better linearity of the positive slope or the negative slope of the triangular wave than the held voltages v 1 and v ₂ . 2 switch 308b to select and output the first gate signal 4.
The first timing signal 203 is input to the sixth flip-flop 315 to the ninth flip-flop 318 to which the fourth gate signal 411 is input, respectively, and the signals S, T, and
U, V first discrimination signal 412, second discrimination signal 41
3. From the third discrimination signal 414 and the fourth discrimination signal 415, the first switch 308a is activated by the logical sum of the first discrimination signal 412 and the second discrimination signal 413; 2nd logical sum
The switch 308b is closed when the logical sum becomes H logic, and the voltage connected to the switch is output and converted into a digital value by the first A/D conversion means 110a. As a result, from the first timing signal 203 indicating the starting end of the signal under test 201 to the first
The fractional time Δt ₁ until the clock signal 205 is the first
When the discrimination signal 412 is H logic, T ₀ ×v ₁ /v ₀ is proportional to the converted digital value, and when the second discrimination signal 413 is H logic, T ₀ (1 −v ₁ /v ₀ ), and when the third discrimination signal 414 is H logic, the converted digital value exceeds v ₀ /2 as T ₀ (v ₂ /v ₀ −1/
2), when it is less than v ₀ /2, T ₀ (v ₂ /V ₀
+1/2), when the fourth discrimination signal 415 is H logic, the converted digital value is v ₀ /2 or less, T ₀ (1/2 - v ₂ /v ₀ ), and it is v ₀ / When it exceeds 2, it is calculated as T ₀ (3/2−v ₂ /v ₀ ).

Next, the method for determining the fractional time Δt ₂ is the same as that for the fractional time Δt _1. When the second timing signal 204 is output, the second sample and hold circuit 108b calculates the voltage v ₃ of the first triangular wave 405a at that time. is held as the second hold voltage 209b in FIG. 2J, and the fourth sample and hold circuit 307b holds the voltage _v4 of the second triangular wave 406b at that time as the fourth hold voltage 406b in FIG. 2K.
From the held voltages v ₃ and v ₄ , the third switch 308c selects the voltage corresponding to T ₀ /4, which is the middle of the positive slope or the negative slope of the two triangular waves, whichever has better linearity. and 4th switch 3
08d, the 10th to 10th flip-flops 319 to 411 to which the first to fourth gate signals 408 to 411 are respectively input are used.
13 The second timing signal 204 is input to the flip-flop 322, and the fifth discrimination signal, sixth discrimination signal 416, sixth discrimination signal 417, and seventh discrimination signal shown in FIG. 2 W, X, Y, and Z obtained from each are obtained. 4
18, from the eighth discrimination signal 419, the fifth discrimination signal 4
16 and the sixth determination signal 417.
Through the gate 325, the third switch 308c,
The fourth switch 308d is closed through the eighth gate 326 which takes the logical sum of the seventh judgment signal 418 and the eighth judgment signal 419, and the sample hold connected to the switch is closed when the logical sum becomes H logic. The voltage held therein is output from the circuit and converted into a digital value by the second A/D conversion means 110b. As a result, the fractional time Δt ₂ between the second timing signal 204 indicating the end of the signal under test 201 and the first clock signal 205 that occurred immediately before it is converted when the fifth discrimination signal 416 is H logic. T ₀ (1−v ₃ /
v ₀ ), when the sixth discrimination signal 417 is H logic, T ₀ · v ₃ /v ₀ is proportional to the converted digital value.
, when the digital value of the seventh discrimination signal 418 converted by H logic exceeds v ₀ /2, T ₀ (3/2
−v ₄ /v ₀ ), and when it is less than v ₀ /2, T ₀ (1/
2-v ₄ /v ₀ ), when the digital value of the eighth discrimination signal 419 converted by H logic is less than v ₀ /2.
T ₀ (1/2+v ₄ /v ₀ ), and when it exceeds v ₀ /2, it is determined as T ₀ (v ₄ /v ₀ −1/2).

By adding the count value T ₀ (n1-1) obtained by the counting means 107 in this way and the fractional times of Δt ₁ and Δt ₂ with the necessary weighting applied to each, the time of the signal under measurement 201 is calculated. The interval Tx can be found. The calculation is performed by the calculation means 111, and the result is displayed on the display 112.

As described above, the time interval Tx of the signal under test 201
To find the remaining fractional times Δt ₁ and Δt ₂ when counted by the first clock signal 205, the phase is, for example,
By using two triangular waves differing by 90 degrees and always using only the voltage near the middle of the triangular waves with good linearity for measurement, time intervals shorter than the first clock signal 205 can be measured with high precision.

Note that the present invention is not limited to the embodiments only, and various applications are possible. For example, the present invention can be used to measure the period and frequency of a signal.

〔Effect of the invention〕

There is a method of measuring time intervals that is shorter than the period of the clock signal using only one clock signal, regardless of the timing of measuring the time interval, and one triangular wave synchronized with it. It is extremely difficult to achieve high accuracy unless the values are improved. By using triangular waves with different phases that are synchronized with the clock signal as in the present invention, it is possible to always use the voltage near the middle of the triangular wave, which has good linearity. It is possible to measure accuracy.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the same configuration.
FIG. 3 is a configuration diagram of the time measuring device before improvement, and FIG. 4 is a time chart for explaining the operation of the same configuration. 101...Input terminal, 102...Timing signal forming circuit, 106...Gate, 107...Counting means, 1
08a, 108b...sample hold circuit, 11
0a, 110b... A/D converter, 111... Arithmetic means, 301... Oscillator, 302-305... Flip-flop, 306a, 306b... Triangular wave forming circuit, 307a, 307b... Sample-hold circuit, 308a-308d... Switch, 309... Flip-flop , 310... counting clock forming means, 311-314... gates, 315-322...
Flip Flop, 323-326...Gate.

Claims (1)

[Claims] 1. A first means for outputting signals indicating the start and end of a time interval to be measured; a second means for generating a reference clock signal having a certain period; and a clock signal having a known period than the reference clock signal. third means for obtaining a first clock signal and a second clock signal having the same period as the clock signal and out of phase with the first clock signal; a fourth means for obtaining a triangular wave synchronized with; a fifth means for holding each voltage of each triangular wave at the beginning and end of the time interval to be measured; and the voltage held by the fifth means. a sixth means for converting the triangular wave that falls within a slope with good linearity into a digital value; a seventh means for counting a signal having a known period between the time intervals to be measured; A time measurement device characterized by comprising: an eighth means for calculating a value obtained by the means and a value obtained by converting the digital value according to the polarity of the slope of the triangular wave by applying necessary weighting. Device.