JPH0424676B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a method for measuring time by enlarging a fraction of the clock period when measuring clock signals. The present invention relates to an applied time measuring device.

(Prior art) As this type of time measuring device, the applicant has developed a third
We also proposed what is shown in the figure. In the figure, 101 is a measured signal input terminal, 102 is a timing signal forming circuit, 103a is a first oscillator, 103b is a second oscillator, 104a is a first counting clock forming circuit, 1
04b is the second clock forming circuit, 105a is the first clock forming circuit.
Counting means, 105b is a second counting means, 106 is a calculation means, 107 is a display, 201 is a signal under measurement,
202 is a reset signal, 203 is a first timing signal, 204 is a second timing signal, 205a is a first clock signal, 205b is a second clock signal, 206a is a first counting clock signal, 206b
is the second counting clock signal.

This operation is performed when the reset signal shown in FIG. 4B is input to the timing signal forming circuit 102, and then the signal under test 201 with the time interval TX shown in FIG. 4A is input to the input terminal 101. 102, the first timing signal 203 in FIG. 4C indicating the rising edge of the signal under test 201 is
Further, the second timing signal 204 shown in FIG. 4D indicating the falling edge of the timing signal 204 is outputted. When the first timing signal 203 is input to the first oscillator 103a, the first clock signal 205a of period T1 shown in FIG. 4E starts to be output. Further, when the second timing signal 204 is input to the second oscillator 103b, the second clock signal 205b having a period T2 shown in FIG. 4F starts to be outputted. During the period from when the first clock signal begins to be output until when the second clock signal 205b is output, the first counting clock signal 206a in FIG. It is detected and output by the clock forming circuit 104a. At this time, the fractional time Δt shown in FIG. 4F remains undetected. This is the second clock signal 205
After b is output, this and the first clock signal 2
05a for the first time, the second
The fourth clock output from the second counting clock forming circuit 104b is equal to the period T2 of the clock signal 205b.
This corresponds to the second counting clock signal 206b in FIG. The first counting clock signal 206a is sent to the first counting means 105a, and the second counting clock signal 206b is sent to the first counting clock signal 206b.
are counted by the second counting means 105b, each weighted and added by the next stage calculation means 106. The results are displayed on the display 107.

The count value of the first counting means 105a is n1, and the second
Assuming that the count value of the counting means 105b is n2, the signal under test 201 is determined as follows: TX=T1×n1+Δt=T1×n1+(T1−T2)×n2.

As mentioned above, when the oscillator that generates the clock signal starts oscillating, the period of the clock signal undergoes a transient change. In addition, it takes a maximum time of "T2 × T1 / (T1 - T2)" to measure fractional time, and to obtain high resolution, it is necessary to reduce the time difference between periods T1 and T2, and then the clock of period T2 Since it takes time for the clock to catch up with the clock with period T1, it has the disadvantage that the measurement time takes an exponential amount of time.

(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and aims to provide a time measuring device that can measure time intervals shorter than the period of a clock signal at high speed and with high resolution. It is something.

[Structure of the Invention] (Means and Effects for Solving Problems) The present invention provides a first signal that outputs a first signal indicating the starting edge of a time interval to be measured and a second signal indicating the ending edge. means for counting clock signals having a known period falling between said first and second signals;
a third means for outputting a triangular wave synchronized with the clock signal; a fourth means for detecting the polarity of the slope of the triangular wave at the time of generation of the first and second signals; A fifth circuit that converts the triangular wave voltage corresponding to the point in time when the second signal is generated into a digital value.
and a sixth means for adding necessary weights to the digital values obtained from the second and fifth means, and is not related to the signal under measurement. By constantly generating one clock signal and using the triangular wave signal generated from it, it is possible to measure time intervals shorter than the clock signal at high speed and with high resolution.

(Example) An example of the present invention will be described below with reference to the drawings. Although FIG. 1 is a block diagram of the same embodiment, parts corresponding to those in FIG. 3 are given the same reference numerals and their explanation will be omitted. In FIG. 1, 301 is an oscillator, 302 is a first flip-flop, 303 is a triangular wave forming circuit, 304 is an AND gate, 305 is a counting means, 306a is a first sample and hold circuit, 306b is a second sample and hold circuit, 30
7a is a second flip-flop, 307b is a third flip-flop, 308a is a first A/D (analog/digital) conversion means, and 308b is a second A/D converter.
Converting means, 309 is an arithmetic means, 401 is a first clock signal, 402 is a second clock signal, 403 is a triangular wave, 404 is a counting clock signal, 405a is a first hold voltage, 405b is a second hold voltage, 406a is a first The discrimination signal 406b is a second discrimination signal.

Oscillator 301 always outputs first clock signal 401 shown in FIG. 2E. From the input terminal 101 to the timing signal forming circuit 102,
A signal under test 201 is input. The timing signal forming circuit 102 generates a first timing signal 203 in FIG. 2B indicating the start timing of the time interval TX of the signal under test 201, and a second timing signal 204 in FIG. 2C indicating the end of the time interval TX. is output at each point in time. The first flip-flop 302 performs frequency division operation. Triangular wave forming circuit 3
03 creates a triangular wave. AND gate 304 takes AND logic with two inputs. The counting means 305 counts the pulses of the counting clock signal 404. First and second sample and hold circuits 306a, 30
6b holds the voltage of the triangular wave 403 at the time when the timing signal is input. The second and third flip-flops 307a and 307b determine the polarity of the slope of the triangular wave 403 at the time the timing signal is output. First and second A/D (analog/digital) conversion means 308a and 308b convert the first and second hold voltages 405a and 405b into digital values. The calculation means 309 weights and adds the obtained values. The display 107 displays the results.

In the operation shown in FIG. 1, the oscillator 301 always outputs the second
A first clock signal 401 with a period T0 shown in FIG.
The frequency is divided by 2, and the triangular wave 40 with the wave height value E0 in Figure 2 G is obtained.
Create 3. The reset signal 202 shown in FIG. 2D is input to the timing signal forming circuit 102, and the time interval TX shown in FIG. 2A is input from the input terminal 101.
When the signal under test 201 is input, the first timing signal 203 indicating the start of the time interval TX of the signal under test 201 is output. The voltage E1 of FIG. 2G, which is the voltage of the triangular wave 403 at this point, is
The sample hold circuit 306a holds it as a first hold voltage 405a. Also, the polarity of the slope of the triangular wave at this time is determined by the first discrimination signal 406a in FIG. 2I at the second flip-flop 307a.
Detected as.

Apart from this, the time interval TX of the signal under test 201
open the AND gate 304 and pass the first clock signal 401 to the counting clock signal 404 of FIG.
get. Further, when the second timing signal 204 in FIG. 2C indicating the end point of the time interval TX of the signal under test 201 is output from the timing signal forming circuit 102, the voltage of the triangular wave 403 at that point in time is outputted from the second timing signal 204 in FIG. The voltage E2 of sample and hold circuit 3
06b, it is held as the second hold voltage 405b. Further, the polarity of the slope of the triangular wave at this time is detected by the third flip-flop 307b as the second discrimination signal 406b in FIG. 2J.

The counting clock signal 404 is counted by a counting means 305. Further, the first hold voltage 405a is the first hold voltage 405a.
The second hold voltage 405b is converted into a digital value by the 1A/D conversion means 308a and the second A/D conversion means 308b, respectively. counting means 305;
The values obtained from the first and second A/D conversion means are weighted, respectively, and addition is performed by the calculation means 309. The results are displayed on the display 107.
The calculations performed by the calculation means 309 are shown below.

It is assumed that the time interval of the signal under test 201 is TX, the peak value of the triangular wave is E0, and the period of the first clock signal is T0. When the polarity of the slope of the triangular wave is negative, the outputs of the second and third flip-flops are H logic, and at that time, the contents of P1 and P2 in the following equation are set to "0". In the opposite case, it is set to "1". Also, the first clock signal 4 that comes first from the rising edge of the signal under test 201
01 is Δt1, and the time between the falling edge of the signal under test 201 and the immediately preceding pulse of the first clock signal 401 is Δt2, and the counting means 30
5 is the value obtained from n1, the first A/D conversion means 30
The value obtained from 8a is n2, and the second A/D conversion means 3
When the value obtained from 08b is n3 and the full scale of A/D conversion is n4 (this value and the value of E0 are assumed to be equal), the time interval TX to be obtained is TX = T0 × n1 + Δt ₁ + Δt ₂ = T0 ×n1+(T0/n4)×｜n4×P1−n ₂ |+
(T0/n4) × |n4×P2−n3| In the above TX formula, the digital values obtained for n1, Δt1, and Δt2 have different meanings, but if these magnitudes have different meanings, the above TX formula cannot be calculated. The process of matching the meanings of the augends is called "weighting." here TX
T0 and T0/n4 of the three addend terms in the equation are "weights" used for the weighting described above. Furthermore, P1 and P2 indicate the polarity of the slope of the triangular wave at both ends of the TX.

As described above, the time interval TX of the signal under test 201
When counted using the first clock signal 401, the remaining fractional times Δt ₁ and Δt ₂ can be obtained at high speed and with high resolution.

Note that the present invention is not limited to the embodiments only, and various applications are possible. For example, the present invention can also be used to measure the period and frequency of a signal.

[Effects of the Invention] As a means of measuring time intervals, there is a method of measuring using two clock signals with different periods (time vernier method). In this method, it is necessary to create a clock signal that rises from the beginning and end of the time interval to be measured, and the precision of the rise time of this clock signal, the counting error due to frequency deviation between the two clock signals, and the measurement time of fractional time are The higher the resolution, the more problematic it becomes. In contrast, the present invention enables measurement to be performed using only one clock signal, which is unrelated to the measurement timing, and one triangular wave synchronized with the clock signal, so that it is possible to speed up the measurement time and obtain high resolution. be.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the same configuration.
FIG. 3 is a configuration diagram of the time measuring device before improvement, and FIG. 4 is a time chart showing the operation of the same configuration. 101... Signal input terminal to be measured, 102... Timing signal forming circuit, 301... Oscillator, 30
2, 307a, 307b... flip-flop,
303... Triangular wave forming circuit, 304... AND gate, 305... Counting means, 306a, 306b
...Sample hold circuit, 308a, 308b
... A/D conversion means, 309 ... calculation means.

Claims (1)

[Claims] 1. A first means for respectively outputting signals indicating the start and end of the time interval to be measured; a second means for obtaining a clock signal having a known period and generated before the time to be measured; a third means for digitally counting the clock signal that enters between the start and end of the time interval to be measured; a fourth means for outputting a triangular wave synchronized with the clock signal; and the time to be measured. fifth means for detecting the polarity of the slope of the triangular wave at the beginning and end of the interval; detecting the voltage of the triangular wave corresponding to the beginning and end of the time interval to be measured; a sixth means for converting each into a digital value; the digital count value obtained by the third means and the digital value obtained by the sixth means into a value converted according to the polarity of the slope of the triangular wave; On the other hand, a time measuring device characterized in that it comprises a seventh means for performing addition calculations with necessary weighting.