JPH04268294A - Boosting circuit - Google Patents

Abstract

PURPOSE:To improve boosting capability by providing non-reversing output level shifters and reversing output level shifters which provide a clock to each capacitor. CONSTITUTION:Output terminals 2 output a boosted output voltage. MOS field effect type transistors C1 to Cn, to which serially connected diodes between the output terminals 2 and a power supply input terminal are connected, and capacitors whose one sides are connected to the mutual connection points, are used with a forward direction charge transfer operation to obtain a boosted voltage. The non-reversing output level shifters and reversing output level shifters, which supply a clock to these capacitors, receive their power supply from the MOS field effect type transistors located in the previous stage. By providing the non-reversing output level shifters and reversing output level shifters, which supply a clock to these capacitors, and by obtaining the power supply of these level shifters from the previous stage NMOS transistor outputs, substrate bias effect is reduced and voltage boosting capability is enhanced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit, and more particularly to a booster circuit that uses MOS field effect transistors and eliminates the substrate bias effect thereof.

0002

2. Description of the Related Art Conventionally, a booster circuit shown in FIG. 4 has been known as a booster circuit used in CMOS integrated circuits and the like. The circuit configuration of this booster circuit is that n diode-connected N-channel MOS transistors (hereinafter referred to as NMOS transistors) N1 to Nn are connected in series in the forward direction from the positive terminal of the power supply 1 to the output terminal 2. It has a configuration in which n capacitors C1 to Cn are connected to each connection point.

In this circuit, one terminal of the capacitors C1 to Cn is alternately driven to the "H" level or "L" level by the clock signal φ and its inverted signal, so that the power supply 1 The input voltage V0 supplied by
is boosted and output as the output voltage Vout.

Here, the boosted voltage ΔV is determined by the number n of NMOS transistor stages, and the output voltage Vout is Vout=V0+ΔV.

[0005] Furthermore, the final stage NMOS transistor Nn
The clamp circuit 3 provided between the output terminal 2 and the output terminal 2 is provided for the purpose of clamping excess voltage in order to always obtain a constant output voltage despite fluctuations in the power supply voltage V0.

[0006]

The conventional booster circuit described above does not have sufficient boosting ability for reasons described later, and its applications may be limited depending on the value of the power supply voltage V0.

For example, when the power supply voltage V0 is 1.5 to 3.0
When the voltage is low (V), it cannot be boosted to about 25V, and E2 PROM (Electrical Eraser PROM)
It cannot be used as a write/erase voltage for BLE PROM). The explanation is below.

Now, in FIG. 4, the power supply voltage is V0, and the absolute value of the voltage applied via the capacitors C1 to Cn is |
Vφ|, the threshold voltage of the NMOS transistors N1 to Nn is VT, and the number of NMOS transistor stages is n, the output voltage Vn of the booster circuit is theoretically expressed by the following equation. Vn =V0 +n(|Vφ|-VT)

(1) However, in reality, the threshold voltage VT of the NMOS transistor in each stage is not constant. Since the input voltage from the previous stage, that is, the back gate voltage, increases as the number of boosting stages increases, it differs from stage to stage due to the substrate bias effect.

Generally, when the substrate effect coefficient is Vb, the substrate Fermi level is φb, the back gate voltage is Vbg, and the substrate effect index is N, the threshold voltage VT of an NMOS transistor is expressed as follows. VT =Vto+Vb (φb +Vbg)N

It is expressed as (2). However, Vto is a constant.

As can be seen from equation (1), the output voltage is NM
It increases as the number of OS transistor stages increases. However, since the back gate voltage increases at the same time,
It can be understood from equation (2) that the threshold voltage of the NMOS transistor also increases.

[0011] Therefore, the boost voltage per stage is
The higher the number of transistor stages, the smaller the size becomes.

As an example, a case where the power supply voltage V0 is 5.0V and a case where the power supply voltage V0 is 1.5V will be compared.

First, consider the case where the power supply voltage V0=5.0V. At this time, for example, Vto=0.04V,
Vb =0.79, φb =0.7eV, and N=0.5.

Under the above conditions, equation (2) becomes

00
15]

It is expressed as follows. The back gate voltage Vbg in the first stage is equal to the power supply voltage V0, which is 5.0V. Substituting this value into equation (3), the threshold voltage VT1 of the first stage NMOS transistor N1 is VT1≒1.9
It is required to be 3V.

[0017] This value is V1 = 5.0 + (5.0 - VT
1), the output voltage V1 of the first stage NMOS transistor N1 is obtained as 8.07V.

Similarly, when the output voltages of each stage are determined and expressed in a graph, the results shown by curve A in FIG. 5 are obtained. Figure 5
1 is a diagram showing the relationship between the number of stages of NMOS transistors and the output voltage of each stage.

From FIG. 5, it can be seen that an output voltage of 25.79V is obtained when the number of stages of NMOS transistors is 12.

Next, consider the case where the power supply voltage V0=1.5V. In this case, Vto=0.50V, Vb=0
．． 24V, φb =0.7eV, and N=0.5.

Substituting these values into equation (2), we get

0
022]

[0023] Based on this, the power supply voltage is 5.0
Similarly to the case of V, the output voltage of each stage was determined and plotted, and the result is shown by curve B in FIG.

When the power supply voltage V0 was 5V, the output voltage achieved at the 12th stage was 25.79V, whereas when the power supply voltage was 1.5V, the output voltage reached 7.79V at the 12th stage. 1
It can be seen that only 0V is obtained.

[0025] Also, from equation (4), back gate voltage Vb
When g is approximately 16.69V, the threshold voltage VT of the NMOS transistor reaches 1.5V, and |Vφ|-VT
= 0, so no matter how many stages of NMOS transistors are added, the output voltage will be 1.
It will not be boosted beyond 6.69V.

Therefore, when the power supply voltage is 1.5V,
It is not possible to boost the voltage up to 25V, and this booster circuit is
2. This means that it cannot be used as a booster circuit for writing and erasing PROM.

SUMMARY OF THE INVENTION An object of the present invention is to improve the drawbacks of the conventional booster circuit as described above, and to provide a booster circuit that is not affected by the body bias effect and has greater capacity than the conventional booster circuit.

[0028]

[Means for Solving the Problems] The booster circuit of the present invention includes a diode-connected MOS field effect transistor connected in series between an output terminal for outputting a boosted output voltage and a power supply input terminal, and a mutual communication between the two. A booster circuit that obtains a boosted voltage by a forward charge transfer operation with a capacitor whose one end is connected to a connection point, the booster circuit having a non-inverting output level shifter and an inverting output level shifter that supply a clock to the capacitor,
The non-inverting output level shifter and the inverting output level shifter are characterized in that power is supplied from the output of the MOS field effect transistor in the preceding stage.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The difference between this embodiment and the conventional booster circuit shown in FIG. 4 is that in this embodiment, the capacitance C1 is
-Cn are provided with non-inverted output level shifters NL1 to NLn or inverted output level shifters IL2 to ILn for inputting clocks.

The non-inverting output level shifter and the inverting output level shifter are arranged so that the clocks input to the capacitances of adjacent stages have opposite phases to each other, and the phase relationship of these clocks is different from that in the conventional booster circuit. is the same as

However, in this embodiment, the amplitude of the clock input to the capacitances C1 to Cn of each stage is equal to that of the previous stage N.
so that it has the same value as the output voltage of the MOS transistor,
The power for each non-inverting output level shifter and inverting output level shifter is taken from the output side of the NMOS transistor at the previous stage.

As the above-mentioned non-inverting output level shifter and inverting output level shifter, for example, one having a circuit configuration as shown in FIG. 2 is used.

This circuit has a PMOS transistor QP1 and an NMOS transistor connected between the high-level power supply terminal 4 and the ground terminal 5.
Transistor QN1 is connected in series, and PMOS
The transistor QP2 and the NMOS transistor QN2 are connected in series, and are connected to each other in a flip-flop configuration.

As an input signal, the signal φ0 shown in FIG.
is input to input terminal 6. The signal is input to the gate of the NMOS transistor QN1 via the inverter 7, and is also input to the gate of the NMOS transistor QN2 via the two-stage inverters 7 and 8.

The output of this circuit is the connection point between PMOS transistor QP1 and NMOS transistor QN1 or P
MOS transistor QP2 and NMOS transistor QN
It is taken out from the connection point of 2.

This circuit operates as a non-inverting output level shifter when the output is output from the output terminal 9. Furthermore, when the output is output from the output terminal 10, it operates as an inverted output level shifter.

Note that, as described above, the output voltage (V1 to Vn-1
) is given. On the other hand, the power supply of inverters 7 and 8 is
It is supplied from the power supply 1 in FIG.

The circuit operation of this embodiment will be explained below. This embodiment has a configuration in which the output voltage of the NMOS transistor in the previous stage is supplied to the capacitor in the next stage. Therefore,
The output voltage Vm at any m-th stage is the N of that stage.
If the threshold voltage of the MOS transistor is VTm and the output voltage of the previous stage is Vm-1, then Vm = Vm-1 + (Vm-1 - VTm)
=2Vm-1 -VTm

It is expressed as (5). VTm at this time is VTm=Vto+Vb (φb +Vm-1)N

(6).

For example, power supply voltage V0 = 1.5V, Vt
o=0.50V, Vb=0.24, φb=0.7e
When V, N = 0.5, the first stage NMOS transistor N1
From equation (6), the threshold voltage VT1 of

[0041]

Therefore, the output voltage V1 of the first stage is:
From equation (5), V1 = 2 x 1.5 - 0.86 = 2.14V.

This value is the same as the output voltage of the first stage NMOS transistor in a conventional booster circuit. However, in this embodiment, since the output voltage of the first stage, that is, 2.14V, is applied to the capacitor C2 of the next stage, the second stage
The output voltage V2 of the NMOS transistor N2 in the stage is
From equations (5) and (6),

[0044]

[0045]

Similarly, the output voltages of each stage were determined and plotted, and the results are shown by curve C in FIG. Power supply voltage V0 is 1
．． Even though the output voltage is 5V, an output voltage of 25V or more is achieved in 6 stages. This is half the number of stages compared to the conventional booster circuit, which required boosting in 12 stages to obtain the same output voltage, and it can be seen that the boosting capability of this embodiment is extremely large. .

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram of this embodiment.

This embodiment differs from the first embodiment shown in FIG. 1 in that the boost stage is divided into two boost blocks.

In the first half of the boosting block (first stage to kth stage), as in the first embodiment, the power supply of the non-inverting output level shifter and the inverting output level shifter is connected to the NMO of the previous stage.
It is taken from the output terminal of the S transistor. As mentioned above, this is the capacitance C1 to Ck belonging to this boost block.
This is to ensure that the amplitude of the clock input to the circuit has the same value as the output voltage of the NMOS transistor at the previous stage.

On the other hand, the second half boosting block ((k+1)th
(from the stage to the nth stage), the power supply for the non-inverting output level shifter and the inverting output level shifter is common, and the power supply is the output terminal of the first half boosting block, that is, the output terminal of the NMOS transistor Nk of the last stage of the first half boosting block. It is taken from.

The operation of this embodiment will be described below. In this embodiment, the first half of the boost block has a configuration in which the output voltage of the NMOS transistor in the previous stage is supplied to the capacitor in the next stage, as in the first embodiment, and is explained in the first embodiment. The pressure is increased as described above. Then, in the second half boosting block, boosting is performed based on the voltage obtained in the first half boosting block.

For example, when boosting is started from the power supply voltage V0 = 1.5V, the boosted voltage reaches 5.78V at k=3rd stage. Then, assuming that the stage k = 4th and subsequent stages are the boost blocks in the latter half, the absolute value |Vφ| of the voltage applied via the capacitor is constant at |Vφ| Therefore, the rate of increase in the output voltage is lower than in the first embodiment. This situation is shown by curve D in FIG.

In this embodiment, the first half of the boost block raises the clock voltage |Vφ| to a level where it is dissociated from the range that is largely affected by the body bias effect, and then the clock voltage |Vφ| is taken over to the second half of the boost block. , which prevents excessive pressurization.

[0054]

[Effects of the Invention] As explained above, according to the present invention,
In a booster circuit that obtains a boosted voltage through a forward charge transfer operation, a non-inverting output level shifter and an inverting output level shifter that supply clocks to each capacitor are provided, and the power supply for these level shifters is taken from the output of the NMOS transistor in the previous stage, so that the substrate Since the influence of the bias effect can be reduced, the boosting capability can be made larger than in the conventional case.

Therefore, the booster circuit of the present invention can sufficiently generate an output voltage of about 25V even when the power supply voltage is as low as 1.5 to 3.0V. E2 PRO that could not be used
It can be applied to a wide range of applications, such as being used for M.

Furthermore, since the booster circuit of the present invention has much higher boosting efficiency than conventional booster circuits, it is possible to significantly reduce the number of stages in the booster block compared to the conventional one, and therefore, the circuit efficiency is reduced. The number of elements, especially the capacitance, can be reduced. This has a great effect on reducing the chip size when integrated into an LSI.

Furthermore, in the booster circuit according to the invention as claimed in claim 1, the boosted voltage per stage increases as the number of stages increases, so the design may become difficult as the number of stages increases. According to the second aspect of the invention, it is effective to divide the boost stage into several boost blocks, and after obtaining the minimum required boost voltage, use this as a constant clock voltage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an example of a non-inverting output level shifter and an inverting output level shifter used in the first embodiment.

FIG. 3 is a circuit diagram of a second embodiment of the invention.

FIG. 4 is a circuit diagram of a conventional booster circuit.

FIG. 5 is a theoretical curve showing the relationship between the number of boosting stages and the output voltage of the first and second embodiments of the present invention and the conventional boosting circuit.

[Explanation of symbols]

1 Power supply 2, 9, 10 Output terminal 3 Clamp circuit 4 High-level power supply terminal 5 Ground terminal 6 Input terminal 7, 8 Inverter

Claims (2)

[Claims] [Claim 1] A diode-connected MOS field effect transistor connected in series between an output terminal that outputs a boosted output voltage and a power supply input terminal, and a capacitor that has one end connected to the mutual connection point. The booster circuit obtains a boosted voltage through a forward charge transfer operation, and includes a non-inverting output level shifter and an inverting output level shifter that supply a clock to the capacitor, and the non-inverting output level shifter and the inverting output level shifter are configured such that the power supply is connected to the previous stage. A booster circuit characterized in that it is supplied from the output of a MOS field effect transistor. 2. A diode-connected MOS field effect transistor connected in series between an output terminal that outputs a boosted output voltage and a power supply input terminal, and a capacitor that has one end connected to a mutual connection point thereof; The booster circuit includes a non-inverting output level shifter and an inverting output level shifter that supply a clock to the capacitor, and obtains a boosted voltage by a forward charge transfer operation, wherein the series circuit of the MOS field effect transistor and the capacitor is connected to a plurality of booster voltages. The non-inverting output level shifter and the inverting output level shifter included in the boosting block that are divided into blocks and connected to the power supply input terminal are supplied with power from the output of the MOS field effect transistor in the previous stage, and are included in the other boosting blocks. A booster circuit characterized in that the non-inverting output level shifter and the inverting output level shifter are supplied with power from the output of a boosting block preceding each boosting block.