JPH04268656A - Data transfer device - Google Patents

Abstract

PURPOSE:To increase the number of degrees of freedom of the system constitution without increasing the amount of hardware by providing each of a channel controller and channel devices with a control storage and rewriting a line control microprogram at the time of staring a line with respect to a data transfer device provided with plural channels. CONSTITUTION:A channel controller CHC 1 is provided with a main control storage MCS 11. A channel device 21 is provided with a channel control storage CCS 211 and plural devices or adapter mounting slots for lines. When the system is started, the fundamental part of the microprogram is stored in the MCS 11. When the CHC 1 gets ready, the fundamental part of the microprogram is stored in the CCS 211, and an OS is started. Thus, a control microprogram is written in each CCS 211 from a memory area having control software when a device or a line is started.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer apparatus for an information processing system, and more particularly to a data transfer apparatus capable of connecting various devices or lines.

0002

2. Description of the Related Art Conventionally, this type of data transfer device has a plurality of channels (abbreviated as CH) 21 to 2n and a channel control device (abbreviated as CHC) 1 for controlling the channels, as shown in FIG.
Each CH 21 to 2n connects to the peripheral control device (P
(abbreviated as CU)) 31 to 3n. PCU31～
3n controls various device lines 51 to 5m as shown in the figure. At this time, since CH21~2n is not microprogram controlled but merely supports the protocol of interface 41~4n, PCU31~3n
For example, an FW or SW that supports the line protocol is required on the side. Further, a control storage (abbreviated as CS) 11 on the CHC side is not connected to a memory access path 12, but is only connected to a service processor (abbreviated as SUP) 6 via an interface 15. Therefore, a microprogram is written into the CS 11 depending on the processing speed of the SUP 6.

[0003] Also, operating system software (abbreviated as OS) on a memory device (not shown) is installed on CHC1 and CH2 depending on the system configuration when the system is started up.
1 to 2n, PCU31 to 3n and device, line 51
~5n was configured to initialize.

0004

[Problems to be Solved by the Invention] Since the conventional data transfer device described above does not have firmware (FW) or software (SW) to control devices and lines, it is necessary to provide the function on the CPU side and In particular,
As a system, there was an increase in HW and SW. Also CH
Regarding loading the microprogram to the CS of the C part, the S
It depends on the performance of the UP, and the current SUP performance is extremely slow compared to data transfer (~Is), so it is loaded only when the system is initialized. All routines had to be resident in the CS, which increased the amount of hardware required for the data transfer device.

[0005] Regarding the degree of freedom in system configuration, since the interfaces 41 to 4n are each unique, it is necessary to replace the CH and PCU interface ports, and there is a drawback that basically large-scale system changes cannot be made. there were.

[0006]

[Means for Solving the Problems] A data transfer device of the present invention includes a channel control device and a control storage that can be partially written to each channel device, a write path from a memory access path to the control storage, and a control storage write path. The channel device section is equipped with slots for mounting adapters for multiple devices or lines, and when one device or line is activated, the microprogram is transferred from the memory area of each control software to each control storage. Configured to write.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, one embodiment of the present invention is a channel controller (CHC).
1 is a data transfer device connected to a plurality of channel devices (CH) 21 to 2n via a memory access path 12, and the channel control device (CHC) includes a main control storage (MCS) 11 and a main control storage. Storage write control circuit 13 and write path 14
Each channel device includes channel control storage (CCS) 211 to 2n1, channel control storage write control circuits 212 to 2n2, write paths 213 to 2n3, and device adapter mounting slot 2.
14-2n4 are present. Main control storage 1 and channel control storage 211 to 2n1
The inside is divided into a plurality of areas as shown in the figure, and writing in each area is possible under the control of each write control circuit.

At the time of system startup, since there is no OS, the service processor (SUP) (not shown) prepares microprogram data for each control storage in a memory device in its own area, and first writes the main control storage write control circuit. 13 to transfer data to the main control storage 11 in an output transfer format using the access path 12 and store it therein. The microprogram data stored in one area of the main control storage 11 is only the basic part. When the basic part is stored in the main control storage 11 and the channel control device becomes ready, the microprogram in the main control storage writes to each channel control storage write control circuit 212.
~2n2 to send out each channel control storage microprogram data on the memory in the form of output transfer using the memory access path 12. The microprograms sent at this time are only the device processing microprograms necessary for starting the OS.

[0010] When a microprogram is loaded into each control storage and the device becomes ready as a data transfer device, the OS is started up and the OS tries to confirm the ready state of each device. At this time, the OS prepares the microprogram data of the individual control section of each device in its own area, and transfers it to the main control storage and channel control storage in output transfer format.
Store it. However, channel control storage data for devices used when starting the OS and the main control storage basic unit are not sent. Although the area division of each control storage and the number of device-specific parts do not necessarily match, the number of divided areas is generally smaller, and the latest program uses the CACHE type or FIFO type as the writing method of the control storage part. Each write control unit controls it so that it resides permanently.

[0011] In this way, the necessary control microprograms are rewritten one after another in each control storage at the time of an I/O occurrence event, that is, startup, and the readiness of the device is confirmed. When all devices are confirmed to be ready, the system becomes ready and the AP starts operating. At this time, for example, if the line 72 is activated to the channel control storage 211 in which the control microprogram for the device 71 disk device is stored, the channel control storage and the main control storage are transferred from the area of the line control OS as described above. After outputting and transferring the microprogram data, the actual line 71 is activated. Therefore, each software transfer takes a minute longer than normal I/O for each output transfer, but device startup time is usually much larger than writing part of a microprogram, so it can be ignored. . Furthermore, it is also possible to configure a very critical device so that the microprogram resides therein. (Channel in FIG. 2n) Furthermore, the system configuration can be easily changed by simply changing the mounting of each device adapter 214 to 2n4, and the OS rewrites the microprogram as described above.

0012

As explained above, the present invention enables writing of microprograms into each control storage section of a data transfer device to be controlled by the OS, and also enables protocol control within the channel control storage to be controlled by each interface. By rewriting the microprogram in each control storage when O is started, HW
It is possible to provide a data transfer device with a high degree of freedom in system configuration without any increase.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional data transfer device.

[Explanation of symbols]

1 Channel control unit (CHC) 6 Service processor 11 Main control storage (MCS)
12 Memory access path 13 Memory control storage write control circuit 14 Main control storage write path 15 Write path to CS 21 to 2n Channel device (CH) 31 to 3n
PCU 41~4n Each interface 51~5n Each device 211~2n1 Channel control storage (CCS) 212~2n2 Channel control storage write control circuit 213~2n3 Channel control storage write path

Claims (1)

[Claims] Claim 1: A data transfer device that is located between a memory and a device and has a memory access path channel control device and a plurality of channel devices, a control storage that can be partially written to each of the channel control device and the channel device, and a memory access path. It has a write path from the path to the control storage and a control storage write control circuit, and the channel device section is provided with slots for mounting adapters for multiple devices or lines, and when one device or line is activated, each device or line is A data transfer device characterized in that each control storage device or line control microprogram is written from a memory area of line control software.