JPH0427192Y2 - - Google Patents
Info
- Publication number
- JPH0427192Y2 JPH0427192Y2 JP1984150936U JP15093684U JPH0427192Y2 JP H0427192 Y2 JPH0427192 Y2 JP H0427192Y2 JP 1984150936 U JP1984150936 U JP 1984150936U JP 15093684 U JP15093684 U JP 15093684U JP H0427192 Y2 JPH0427192 Y2 JP H0427192Y2
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- circuit board
- mounting
- connector
- small
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Mounting Of Printed Circuit Boards And The Like (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は電子機器に於けるプリント回路基板の
実装構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a mounting structure of a printed circuit board in electronic equipment.
近年、電子計算機をはじめとする電子機器は半
導体素子の高集積化に伴ない小型、高密度化が図
られるようになり、第４図に示す様に複数個の
LSIパツケージ５をはじめとする電子部品７を搭
載したプリント回路基板１を第２図に示す様にパ
ネルフレーム８を用いて複数枚実装した実装方式
がとられているが、特に、近年LSIパツケージの
集積度は増し、単位面積当りの発熱量は増加の一
途にある。そこで、その対策として第４図に示す
様に放熱フイン６を取付けたパツケージ５が使用
される様になつた。
In recent years, electronic devices such as computers have become smaller and more dense due to the higher integration of semiconductor devices, and as shown in Figure 4, multiple electronic devices have become smaller and more dense.
As shown in Figure 2, a mounting method has been adopted in which a plurality of printed circuit boards 1 on which electronic components 7 including an LSI package 5 are mounted are mounted using a panel frame 8. As the degree of integration increases, the amount of heat generated per unit area continues to increase. Therefore, as a countermeasure to this problem, a package 5 having heat radiation fins 6 attached thereto as shown in FIG. 4 has come to be used.
ところで、これらLSIパツケージ５の実装形態
は第２図のＡ矢視図である第５図に示す様に、プ
リント回路基板によつてａ，ｂ，ｃと種々である
が、各々のプリント回路基板ａ，ｂ，ｃの実装部
品の許容高さは一般に汎用性、規即性をもたせる
ため、すべて等しく、実装される最大高さの部品
を許容できる様になつている。すなわち放熱フイ
ン６を取付けたLSIパツケージ５を最大許容高さ
としているわけである。 By the way, the mounting form of these LSI packages 5 varies depending on the printed circuit board, such as a, b, and c, as shown in FIG. In order to generally provide versatility and regularity, the permissible heights of the mounted components a, b, and c are all the same, allowing for components of the maximum height to be mounted. In other words, the maximum allowable height of the LSI package 5 to which the heat dissipation fins 6 are attached is set.
そのため、第５図に示す様に最大高さのLSIパ
ツケージ５が数個のｂタイプや、搭載されないｃ
タイプにおいては、許容実装スペース内に余分な
スペースＳ１，Ｓ２が空き、従つて無駄の多い実
装形態をなすという欠点があつた。
Therefore, as shown in Fig. 5, the LSI package 5 with the maximum height is installed in several B type packages and in C type packages that are not mounted.
This type has the disadvantage that extra spaces S1 and S2 are left in the allowable mounting space, resulting in a wasteful mounting form.
本考案の目的は前記欠点を排し、より高密度な
プリント回路基板の実装構造を提供することにあ
る。 An object of the present invention is to eliminate the above-mentioned drawbacks and provide a higher density printed circuit board mounting structure.
上記目的を達成するため、本考案によるプリン
ト回路基板の実装構造においては、第１のプリン
ト回路基板と、第２の小型のプリント回路基板
と、コネクタとを有し、予め定められた間隔を保
つて複数の第１のプリント回路基板をパネルフレ
ームに列状に実装するプリント回路基板の実装構
造であつて、
パネルフレームに実装された各第１のプリント
回路基板相互間の間隔は、該第１のプリント回路
基板に実装される実装部品の最大許容高さを基準
として設定されたものであり、
第１のプリント回路基板は、背の低い実装部品
から背の高い実装部品まで任意に実装するもので
あり、
第２の小型プリント回路基板は、背の低い実装
部品を実装し、第１のプリント回路基板上の背の
低い実装部品上にまたがつて該第１のプリント回
路基板上に支持させるものであり、パネルフレー
ムへの実装に際しては、各第１のプリント回路基
板の列間の空きスペース部分に設置されるもので
あり、
コネクタは、パネルフレームから第１のプリン
ト回路基板への信号授受及び電源供給を行うもの
と、第１のプリント回路基板を通して第２の小型
プリント回路基板へ信号授受及び電源供給を行う
ものとの２種類である。
In order to achieve the above object, the printed circuit board mounting structure according to the present invention has a first printed circuit board, a second small printed circuit board, and a connector, and maintains a predetermined interval. A printed circuit board mounting structure in which a plurality of first printed circuit boards are mounted in a row on a panel frame, wherein the distance between each of the first printed circuit boards mounted on the panel frame is The first printed circuit board is set based on the maximum allowable height of components mounted on the printed circuit board, and the first printed circuit board is one that can be arbitrarily mounted from short to tall components. The second small printed circuit board has a short mounting component mounted thereon, and is supported on the first printed circuit board by straddling the short mounting component on the first printed circuit board. When mounted on the panel frame, the connector is installed in the empty space between the rows of each first printed circuit board, and the connector is used for transmitting and receiving signals from the panel frame to the first printed circuit board. There are two types: one that performs power supply and one that sends and receives signals and supplies power to a second small printed circuit board through the first printed circuit board.
（作用）
背の低い部品は、第１のプリント回路基板と、
該基板に取付けられた第２の小型プリント回路基
板とに２段に実装され、各段の第１のプリント回
路基板間に形成される空きスペースが減少して部
品の高密度の実装が実現される。(Function) The short component is a first printed circuit board,
The components are mounted in two stages on a second small printed circuit board attached to the board, and the empty space formed between the first printed circuit boards in each stage is reduced to realize high-density mounting of components. Ru.
次に、本考案の実施例について図面を参照して
詳細に説明する。
Next, embodiments of the present invention will be described in detail with reference to the drawings.
第１図において、本考案のプリント回路基板の
実装構造は、LSIパツケージ５を始めとする電子
部品７を搭載した基準となる第１のプリント回路
基板１と、複数個の第１のプリント回路基板各々
の信号授受及び電源の供給を行なうコネクタ３
と、第１のプリント回路基板１同様複数個の電子
部品７を搭載した第２の小型プリント回路２と、
第１のプリント回路基板１と第２のプリント回路
基板２を電気的に接続するコネクター４によつて
構成され、特に第２の小型プリント回路基板２は
基準となる第１のプリント回路基板１の電子部品
の実装許容スペース内の空きスペースに積層設置
するものである。本考案の回路基板を使つた実装
例を第３図に示す。 In FIG. 1, the mounting structure of the printed circuit board of the present invention includes a reference first printed circuit board 1 on which electronic components 7 including an LSI package 5 are mounted, and a plurality of first printed circuit boards. Connector 3 for sending and receiving each signal and supplying power
and a second small printed circuit 2 on which a plurality of electronic components 7 are mounted like the first printed circuit board 1,
It is constituted by a connector 4 that electrically connects the first printed circuit board 1 and the second printed circuit board 2. In particular, the second small printed circuit board 2 is connected to the first printed circuit board 1 as a reference. They are stacked and installed in empty spaces within the allowable mounting space for electronic components. An example of mounting using the circuit board of the present invention is shown in FIG.
本図において、ｂ，ｃタイプが本考案の適用例
であり、ａタイプは本考案を必要としない理想的
な実装例である。 In this figure, types b and c are examples of application of the present invention, and type a is an ideal implementation example that does not require the present invention.
ｂタイプのプリント回路基板は第１のプリント
回路基板１の、放熱フイン６を取付けた背の高い
LSIパツケージ５が搭載されていない空きスペー
スとなる部分に、背の低い電子部品７を搭載した
第２の小型プリント回路基板２を積層設置したも
のである。また、ｃタイプのプリント回路基板は
第１のプリント回路基板１にすべて高さの低い電
子部品７が搭載された場合のもので、上部空きス
ペースとなる部分に第２のプリント回路基板２を
実装したものである。 A type b printed circuit board is a first printed circuit board 1 with a tall structure on which heat dissipation fins 6 are attached.
A second small printed circuit board 2 on which a short electronic component 7 is mounted is stacked and installed in the empty space where the LSI package 5 is not mounted. In addition, the c-type printed circuit board is one in which all low-height electronic components 7 are mounted on the first printed circuit board 1, and the second printed circuit board 2 is mounted in the upper empty space. This is what I did.
第３図から明らかなように、本考案のプリント
回路基板の実装構造をとることによつて、従来空
きスペースとなつていた実装許容スペース部を有
効に利用してプリント回路基板の実装間隔を変え
ることなく、より高密度な実装構造をとることが
できる。 As is clear from Fig. 3, by adopting the mounting structure of the printed circuit board of the present invention, the mounting allowable space portion, which was previously a vacant space, can be effectively utilized and the mounting spacing of the printed circuit board can be changed. A higher-density mounting structure can be achieved without this.
本考案には以上説明した様に、第２のプリント
回路基板を基準となる第１のプリント回路基板の
空きスペースに実装するようにしたため、空きス
ペースを有効利用してより高密度に電子部品をプ
リント回路基板に実装できる効果を有するもので
ある。
As explained above, in the present invention, the second printed circuit board is mounted in the empty space of the first printed circuit board, which is the standard, so the empty space can be used effectively and electronic components can be mounted at a higher density. It has the effect of being able to be mounted on a printed circuit board.
第１図は本考案の一実施例を示すプリント回路
基板の外観図、第２図は複数個のプリント回路基
板を実装したユニツトの外観図、第３図は本考案
による実装状態を示す第２図のＡ矢視図、第４図
は従来のプリント回路基板の外観図、第５図は従
来例による実装状態を示す第２図のＡ矢視図であ
る。
１……第１のプリント回路基板、２……第２の
小型プリント基板、３，４……コネクタ、５……
LSIパツケージ、６……放熱フイン、７……電子
部品。
Fig. 1 is an external view of a printed circuit board showing an embodiment of the present invention, Fig. 2 is an external view of a unit on which a plurality of printed circuit boards are mounted, and Fig. 3 is an external view of a unit in which a plurality of printed circuit boards are mounted. 4 is an external view of a conventional printed circuit board, and FIG. 5 is a view taken along arrow A in FIG. 2, showing a mounting state according to the conventional example. 1... First printed circuit board, 2... Second small printed circuit board, 3, 4... Connector, 5...
LSI package, 6...heat dissipation fin, 7...electronic component.
Claims (1)
ント回路基板と、コネクタとを有し、予め定めら
れた間隔を保つて複数の第１のプリント回路基板
をパネルフレームに列状に実装するプリント回路
基板の実装構造であつて、 パネルフレームに実装された各第１のプリント
回路基板相互間の間隔は、該第１のプリント回路
基板に実装される実装部品の最大許容高さを基準
として設定されたものであり、 第１のプリント回路基板は、背の低い実装部品
から背の高い実装部品まで任意に実装するもので
あり、 第２の小型プリント回路基板は、背の低い実装
部品を実装し、第１のプリント回路基板上の背の
低い実装部品上にまたがつて該第１のプリント回
路基板上に支持させるものであり、パネルフレー
ムへの実装に際しては、各第１のプリント回路基
板の列間の空きスペース部分に設置されるもので
あり、 コネクタは、パネルフレームから第１のプリン
ト回路基板への信号授受及び電源供給を行うもの
と、第１のプリント回路基板を通して第２の小型
プリント回路基板へ信号授受及び電源供給を行う
ものとの２種類であることを特徴とするプリント
回路基板の実装構造。[Claims for Utility Model Registration] A panel includes a first printed circuit board, a second small printed circuit board, and a connector, and a plurality of first printed circuit boards are connected to each other at predetermined intervals. In the mounting structure of printed circuit boards mounted in a row on a frame, the distance between each first printed circuit board mounted on the panel frame is the distance between the mounted components mounted on the first printed circuit boards. It is set based on the maximum allowable height, and the first printed circuit board is used to mount any components from short to tall, and the second small printed circuit board is , a short mounting component is mounted and supported on the first printed circuit board by straddling the short mounting component on the first printed circuit board, and when mounting on the panel frame, , the connector is installed in the empty space between the rows of each first printed circuit board, and the connector is for sending and receiving signals and supplying power from the panel frame to the first printed circuit board; A printed circuit board mounting structure characterized in that there are two types: one in which signals are sent and received and power is supplied to a second small printed circuit board through the printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984150936U JPH0427192Y2 (en) | 1984-10-05 | 1984-10-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984150936U JPH0427192Y2 (en) | 1984-10-05 | 1984-10-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6165791U JPS6165791U (en) | 1986-05-06 |
| JPH0427192Y2 true JPH0427192Y2 (en) | 1992-06-30 |
Family
ID=30709066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984150936U Expired JPH0427192Y2 (en) | 1984-10-05 | 1984-10-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0427192Y2 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5517513Y2 (en) * | 1973-12-25 | 1980-04-23 | ||
| JPS5512472U (en) * | 1978-07-12 | 1980-01-26 | ||
| JPS6234474Y2 (en) * | 1979-09-05 | 1987-09-02 | ||
| JPS6138217Y2 (en) * | 1981-05-26 | 1986-11-05 |
-
1984
- 1984-10-05 JP JP1984150936U patent/JPH0427192Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6165791U (en) | 1986-05-06 |
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