JPH0442891Y2 - - Google Patents

Info

Publication number
JPH0442891Y2
JPH0442891Y2 JP7228786U JP7228786U JPH0442891Y2 JP H0442891 Y2 JPH0442891 Y2 JP H0442891Y2 JP 7228786 U JP7228786 U JP 7228786U JP 7228786 U JP7228786 U JP 7228786U JP H0442891 Y2 JPH0442891 Y2 JP H0442891Y2
Authority
JP
Japan
Prior art keywords
lines
transformers
magnetic force
data channel
mutual interference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP7228786U
Other languages
Japanese (ja)
Other versions
JPS62184711U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7228786U priority Critical patent/JPH0442891Y2/ja
Publication of JPS62184711U publication Critical patent/JPS62184711U/ja
Application granted granted Critical
Publication of JPH0442891Y2 publication Critical patent/JPH0442891Y2/ja
Expired legal-status Critical Current

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  • Housings And Mounting Of Transformers (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【考案の詳細な説明】 〔概要〕 プリント基板にデータチヤンネルのトランスを
複数個隣接して実装する構造であつて、隣接する
トランスから発生する磁力線の相互干渉により回
路特性の低下を防止するために、磁力線が相互に
直交するように配置して、磁力線の相互干渉を減
少せしめることにより、回路特性が向上する。
[Detailed explanation of the invention] [Summary] This is a structure in which multiple data channel transformers are mounted adjacently on a printed circuit board, in order to prevent deterioration of circuit characteristics due to mutual interference of magnetic lines of force generated from adjacent transformers. The circuit characteristics are improved by arranging the lines of magnetic force so as to be orthogonal to each other and reducing mutual interference of the lines of magnetic force.

〔産業上の利用分野〕[Industrial application field]

本考案は、データチヤンネルのトランスの実装
構造に係り、とくに磁力線の相互干渉を減少せし
めるようにしたデータチヤンネルのトランスの実
装構造に関する。
The present invention relates to a data channel transformer mounting structure, and more particularly to a data channel transformer mounting structure that reduces mutual interference of magnetic lines of force.

近年、電子機器全般に小形、軽量化の要望が強
く、この要望を満足せしめるために電子部品の高
密度実装が余儀なくされ、回路を構成する電子部
品の中で磁力線を発生するトランス等を隣接して
配置すると、磁力線が相互干渉する。
In recent years, there has been a strong demand for smaller and lighter electronic devices in general, and in order to satisfy these demands, electronic components have been forced to be mounted in high density. If the magnetic field lines are placed in parallel, the lines of magnetic force will interfere with each other.

〔従来の技術〕 第2図は、従来のデータチヤンネルのトランス
の実装構造を説明する図で、同図aは要部平面
図、bは分散配置した平面図である。
[Prior Art] FIG. 2 is a diagram illustrating the mounting structure of a conventional data channel transformer, in which a is a plan view of the main part and b is a plan view of a distributed arrangement.

第2図aは、データチヤンネルのプリント基板
1に複数(図面では2個)のトランス2,3を、
その磁力線4が平行する形で隣接せしめて実装す
ると、トランス2,3から発生する磁力線は楕円
形をしており、その楕円形の長手方向すなわち幅
部分同志が重なり、相互干渉エリアはハツチング
部5の如く大きくなる。
Figure 2a shows a plurality of (two in the drawing) transformers 2 and 3 on the printed circuit board 1 of the data channel.
When the lines of magnetic force 4 are mounted adjacent to each other in parallel, the lines of magnetic force generated from the transformers 2 and 3 have an elliptical shape, and the longitudinal direction, that is, the width portion of the ellipse overlaps, and the area of mutual interference is the hatched part 5. It grows like this.

第2図bは、プリント基板1上にトランス2,
3から発生する磁力線の相互干渉を避けるために
分散配置したものである。
FIG. 2b shows a transformer 2 on a printed circuit board 1,
In order to avoid mutual interference of the lines of magnetic force generated from the magnetic field lines, the magnetic field lines are distributed in a dispersed manner.

〔考案が解決しようとする問題点〕[Problem that the invention attempts to solve]

上記従来のデータチヤンネルのトランスの実装
構造にあつては、複数個のトランスをその磁力線
が平行するように実装されているので、磁力線の
一部(第2図aのハツチングで示す部分)が相互
干渉し、回路の特性を低下せしめるので分散配置
(第2図b)すると高密度実装を阻害するという
問題点があつた。
In the conventional data channel transformer mounting structure described above, multiple transformers are mounted so that their lines of magnetic force are parallel, so that some of the lines of magnetic force (the part shown by hatching in Figure 2a) overlap each other. Since they interfere with each other and deteriorate the characteristics of the circuit, there is a problem in that distributing them (FIG. 2b) hinders high-density packaging.

〔問題点を解決するための手段〕[Means for solving problems]

本考案は、上記の問題点を解決するために隣接
するトランスから発生する磁力線の相互干渉を減
少せしめたデータチヤンネルのトランスの実装構
造を提供するものである。
In order to solve the above problems, the present invention provides a data channel transformer mounting structure that reduces mutual interference between magnetic lines of force generated from adjacent transformers.

すなわち、プリント基板1にデータチヤンネル
のトランス2,3を複数個隣接して実装する方法
を、前記隣接するトランス2,3の磁力線4が相
互に直交するように配置したことによつて解決さ
れる。
That is, the problem is solved by mounting a plurality of data channel transformers 2 and 3 adjacent to each other on the printed circuit board 1 so that the lines of magnetic force 4 of the adjacent transformers 2 and 3 are orthogonal to each other. .

〔作用〕[Effect]

上記データチヤンネルのトランスの実装構造
は、隣接するトランスを直交せしめて同間隔で配
置することによつて、トランスから発生する磁力
線の相互干渉エリアが減少し、回路特性が向上す
る。
In the data channel transformer mounting structure, adjacent transformers are orthogonally arranged and arranged at equal intervals, thereby reducing the mutual interference area of magnetic lines of force generated from the transformers and improving circuit characteristics.

〔実施例〕〔Example〕

第1図は、本考案の一実施例を説明する要部平
面図で、第2図と同等の部分については同一符号
を付している。
FIG. 1 is a plan view of essential parts for explaining an embodiment of the present invention, and parts equivalent to those in FIG. 2 are given the same reference numerals.

図において、データチヤンネルのプリント基板
1に複数(図面では2個)のトランス2,3を、
その磁力線4が直交する形で隣接せしめて実装す
ると、トランス2,3から発生する磁力線4は楕
円形状をしており、トランス2の磁力線4の楕円
形の細い先端部が、トランス3の磁力線4の幅方
向の中央部と重なるので、その相互干渉エリア6
はハツチング部の如く小さくなる。
In the figure, a plurality of (two in the drawing) transformers 2 and 3 are installed on the data channel printed circuit board 1.
When mounted so that the lines of magnetic force 4 are perpendicular to each other, the lines of magnetic force 4 generated from the transformers 2 and 3 have an elliptical shape. overlaps with the center in the width direction, so the mutual interference area 6
becomes small like the hatched part.

なお、本実施例では実装するトランスを2個に
ついて説明したが、2個以上複数個にも適用が可
能である。
In this embodiment, two transformers are mounted, but the present invention is also applicable to two or more transformers.

〔考案の効果〕[Effect of idea]

以上の説明から明らかなように、本考案によれ
ば相互干渉エリアが減少して、回路特性が向上す
るとともに、高密度実装に極めて有効である。
As is clear from the above description, according to the present invention, the mutual interference area is reduced, circuit characteristics are improved, and the present invention is extremely effective for high-density packaging.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の一実施例を説明する要部平
面図、第2図は、従来のデータチヤンネルのトラ
ンスの実装構造を説明する図で、aは要部平面
図、bは分散した平面図である。 図において、1はプリント基板、2,3はトラ
ンス、4は磁力線、5,6は相互干渉エリア、を
それぞれ示す。
Fig. 1 is a plan view of the main part explaining one embodiment of the present invention, Fig. 2 is a diagram explaining the mounting structure of a conventional data channel transformer, where a is a plan view of the main part and b is a distributed FIG. In the figure, 1 is a printed circuit board, 2 and 3 are transformers, 4 is lines of magnetic force, and 5 and 6 are mutual interference areas, respectively.

Claims (1)

【実用新案登録請求の範囲】 プリント基板1にトランス2,3を複数個隣接
して実装する方法において、 前記隣接するトランス2,3の磁力線4が相互
に直交するように配置したことを特徴とするトラ
ンスの実装構造。
[Claims for Utility Model Registration] A method of mounting a plurality of transformers 2 and 3 adjacent to each other on a printed circuit board 1, characterized in that the lines of magnetic force 4 of the adjacent transformers 2 and 3 are arranged so as to be orthogonal to each other. The mounting structure of the transformer.
JP7228786U 1986-05-13 1986-05-13 Expired JPH0442891Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7228786U JPH0442891Y2 (en) 1986-05-13 1986-05-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7228786U JPH0442891Y2 (en) 1986-05-13 1986-05-13

Publications (2)

Publication Number Publication Date
JPS62184711U JPS62184711U (en) 1987-11-24
JPH0442891Y2 true JPH0442891Y2 (en) 1992-10-12

Family

ID=30915613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7228786U Expired JPH0442891Y2 (en) 1986-05-13 1986-05-13

Country Status (1)

Country Link
JP (1) JPH0442891Y2 (en)

Also Published As

Publication number Publication date
JPS62184711U (en) 1987-11-24

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