JPH0427232A - Data transmitting/receiving circuit - Google Patents

Abstract

PURPOSE:To simultaneously receive data from the opposite party, while transmitting data by transmitting and receiving the data by one piece of signal line, and discriminating receiving data from the opposite party, when an output of transmitting data is H and L, respectively. CONSTITUTION:An output of a buffer 4b for outputting transmitting data by a serial signal is connected to a signal line through a resistance R1, and a transmission signal Sc and an output voltage VA of a reference voltage output circuit 4g are compared by a comparator 4e. When an output Sa of the buffer 4b is H, receiving data from the opposite party is discriminated. Simultaneously, the signal Sa and an output voltage VB of a circuit 4i are compared, and when the signal Sa of the buffer 4b is L, the receiving data from the opposite party is discriminated. The receiving data which are discriminated, respectively are fetched by AND circuits 4c, 4d and an OR circuit 4h. In such a way, while transmitting the data, data transmitted from the opposite party can be received simultaneously, therefore, both persons for executing a communication can send out data at an arbitrary timing. It is unnecessary to switch the circuit at the time of transmission and at the time of reception.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmitting/receiving circuit that connects communicating devices with a signal line and transmits data using serial signals.

[Prior Art] In recent years, the degree of integration of ICs and LSIs has increased, and the number of pins for inputting and outputting signals has become larger than the size of the integrated circuit chip itself.
It has come to have a large effect on the external size of parts.

Therefore, it is common practice to reduce the size of components by reducing the number of input/output signal lines and the number of pins.

[Problems to be Solved by the Invention] As a method of reducing the number of signals, a method of converting a multi-bit parallel signal into a serial signal and inputting/outputting the signal has been put into practice. This method allows multiple bits of data to be input and output using one line, but requires two signal lines for input and output.

On the other hand, it is conceivable to switch one signal line between data input and output. In this case, there are known methods such as setting the data output timing and input timing in advance in a time-sharing manner, and exchanging control information for switching input and output.

However, the method of setting the input/output timing in a time-sharing manner has a problem in that data cannot be output at arbitrary timings.

On the other hand, the method of exchanging control information requires separate circuits for inputting and outputting the control information and determining the information content.
There was a problem that the circuit was complicated and the cost was high.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a data transmitting/receiving circuit that can transmit data at any timing and has a simple circuit configuration.

[Means for Solving the Problem] To this end, in the first invention, data is transmitted and received using one signal line, and the signal line and the data are transmitted and received.

The output of the data output means that outputs the transmission data as a binary serial signal is connected through a resistor, and the output of the data output means is set to high by comparing the voltage applied to the signal line with one reference voltage. In addition to determining the data received from the other party when the output is at the low level, by comparing the applied voltage with another reference voltage, the data received from the other party when the output is at the low level is determined. The received data that has been determined is retrieved.

Further, in the second invention, the output of the data output means is
A reference voltage that changes to the above 2@ is generated when it is at a high level and when it is at a low level, and by comparing the reference voltage with the voltage applied to the signal, the received data from the other party is determined and retrieved. ing.

[Function] Since it is possible to receive data sent from the other party at the same time as sending data, both parties can send data at any timing, and can switch circuits between sending and receiving, and control information. Since there is no need to exchange data, the circuit configuration becomes simpler.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a block diagram of a microcomputer system to which the data transmitting/receiving circuit of the present invention is applied. In the figure, LS Il is, for example, a CPU, and IC2 is, for example, a peripheral circuit that inputs and outputs data to the outside. Pins P1 to P of LSI1 are connected to pin P of IC2, and pin P4 of LSI1 is connected to each IC2.
are connected to pins P6 of the respective terminals.

Inside the LS II, a data processing circuit 3, three data transmitting/receiving circuits 4, and a clock signal output port 1115 are arranged. All three data transmitting/receiving circuits 4 are the same circuit, and transmitting/receiving signals are input/output via pins P□ to P, respectively. Further, the output of the clock signal output circuit 5 is input to each data transmitting/receiving circuit 4, and the output is input to the pin P4.
It is output from.

A data transmitting/receiving circuit 4 and a data processing circuit 6, which are the same circuits as those on the LS II side, are arranged in the ICZ. Transmission and reception signals are respectively input and output via pin P5, and a clock signal is input from pin PG.

FIG. 2 shows a circuit configuration diagram of a pair of opposing data transmitting/receiving circuits 4. In FIG.
Buffer 4b converts D into a serial signal.
The serial signal is output as a binary voltage signal.

Its output is ANDed with one end of resistor H! It is connected to the single power of Nt4c and the inverting input of AND circuit 4d. The other end of the resistor R1 is connected to one pin P1 of LS II and each of the comparators 4e and 4f.

The output of the reference voltage output circuit 4g is connected to the other input of the comparator 4e, and the output of the comparator 4e is connected to the other input of the AND circuit 4c. The output of the AND circuit 4c is connected to one output of the OR circuit 4h. The output of the reference voltage output circuit 41 is connected to the other input of the comparator 4f, and the output of the comparator 4f is connected to the other input of the AND circuit 4d.

The output of the AND circuit 4d is connected to the other input of the OR circuit 4h. The output of OR circuit 4h is serial/
It is connected to the data input of the parallel conversion circuit 4j.

The clock signal output from the clock signal output circuit 5 is input to a parallel/serial conversion circuit 4a, and is also input to a serial/parallel conversion circuit 4j via an inverter 4k.

With the above configuration, when this computer system starts operating, the clock signal output circuit 5 outputs the signal as shown in FIG. 3(a).
A clock signal CL having a constant period as shown in is output. On the other hand, the data processing circuit 3 on the LS II side and the data processing circuit 6 on the ICZ side each perform predetermined operations asynchronously. The data processing circuit 3 inputs the transmission data SD to the IC 2 to the data transmission/reception circuit 4 as necessary, and the data processing circuit 6 inputs the transmission data SD to the LS II.
is input to the data transmitting/receiving circuit 4 as necessary.

When the parallel/serial conversion circuit 4a receives the transmission data SD, it converts the data bit by bit into a serial signal at the rising timing of the clock signal CLK. The buffer 4b outputs the serial signal as a binary voltage signal. The voltage value of the output signal is IJH#l(
It is assumed that VH1 is “L” (low level) and VL is “L” (low level).

The output of the buffer 4b is output to a signal line via a resistor, and is input to the other party via the signal line. As a result, the transmission signal Sc on the signal line becomes the output signal Sa, Sb
When both are “II”, 5c=Vs, output signal Sa,
When both Sb are "Yes", SC:VL is established. Also, among the output signals Sa and Sb, one is “Hjl” and the other is “II”.
When L It, 5c=(V++VL)/2d.

Therefore, for example, the buffer 4b on the LS II side outputs an output signal Sa as shown in FIG. 3(b), and the buffer 4b on the ICZ side outputs an output signal sb as shown in FIG. 3(C). is output, the above transmission signal S
c becomes a three-value voltage signal as shown in FIG. 3(d).

The reference voltage output circuit 4g outputs a reference voltage VA set lower than the voltage value VH of the gL HII and higher than the voltage value (VH+VL)/2, as shown by the broken line in FIG.
Output. As shown in FIG. 4(e), the comparator 4e outputs a signal of 111'' when the voltage value of the transmission signal Sc is low with respect to the reference voltage VA, and outputs a signal of IIH#l when the voltage value is high.

On the other hand, the reference voltage output circuit 41 outputs a reference voltage V set lower than the voltage value (VH+VL)/2 and higher than the voltage value VL of "L'", as shown by the broken line in FIG.
Output B. As shown in FIG. 4(f), the comparator 4f outputs a signal of "Ln" when the voltage value of the transmission signal Sc is low with respect to the reference voltage Va, and outputs a signal of "1111" when it is high.

The AND circuit 4c outputs the output of the comparator 4e to the OR circuit 4h when the output signal Sa is "H", and the AND circuit 4d outputs the output of the comparator 4f to the OR circuit 4h when the output signal Sa is "L". Output to circuit 4h side.

The OR circuit 4h inputs the input signal to the serial/parallel conversion circuit 4j.

As a result, a signal Sf as shown in FIG. 4(g) is input to the serial/parallel conversion circuit 4j on the LSII side.

The serial/parallel conversion circuit 4j receives the input signal S
f at the falling timing of the clock signal CLK,
By reading each bit as a received data signal, the data signal sb transmitted from the ICZ side is reproduced, as shown in (h) of the figure. Then, the data signal is converted into a parallel signal and output as received data RD.

The data processing circuit 3 executes predetermined processing using the received data RD.

On the other hand, on the IC2 side, similarly to the above, the operation of determining the transmission data on the LSII side is performed using the signal sb and the transmission signal Sc. As a result, the OR circuit 4h outputs a signal sh as shown in (i) of the figure. The serial/parallel conversion circuit 4j reads the signal sh bit by bit and reproduces the transmitted data signal. and,
The data signal is converted into a parallel signal and output as a received data signal RD. The data processing circuit 6 executes predetermined processing using the received data RD.

As described above, in this embodiment, the output of the buffer 4b that outputs transmission data as a serial signal is connected to the signal line via the resistor R1, and the transmission signal Sc on the signal line and the reference voltage output circuit 4g are connected by the comparator 4e. The data received from the other party when the output signal Sa of the buffer 4b is at a high level is determined by comparing the output voltage V^ of the buffer 4b, and the output voltage Va of the reference voltage output circuit 41 is compared by the comparator 4f. The received data from the other party when the output signal Sa of the buffer 4b is at a low level is determined by comparing the received data with
, 4d and an OR circuit 4h.

This makes it possible to simultaneously receive data transmitted from the other party while transmitting data, so both parties can transmit data at any timing. Furthermore, the above configuration simplifies the circuit configuration since there is no need to switch circuits or exchange control information between transmission and reception.

FIG. 4 shows another embodiment of the data transmitting/receiving circuit, in which the same symbols as in FIG. 2 indicate the same parts. The other end of the resistor R1 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the other input of the comparator 41 and one end of the resistor R3, and the other end of the resistor R3 is connected to the output of the reference voltage generating circuit 4m. The output of the comparator 41 is input to a serial/parallel conversion circuit 4j.

With this configuration, as shown in FIG. 5(a), the clock signal output circuit 3 outputs the clock signal CL, and as shown in FIG. 5(b) and (C), the LS I
Output signals Sa, Sb from buffer 4b on I side and IC2 side
Suppose that each is output.

At this time, the transmission signal Sc on the signal line becomes a ternary signal as shown in FIG.

The reference voltage generation circuit 4- sets the output voltage of the buffer 4b to V.
If H and VL, a constant voltage of (V++VL)/2 is output.

As a result, the voltage Vc at the connection point between the resistors R2 and R3 changes so that the output of the buffer 4b becomes "
When the voltage is high, the voltage changes slightly higher than the voltage (VH+VL)/2, and when the voltage is low, the voltage changes slightly lower than that voltage.

The comparator 41 compares the voltage Vc with the transmission signal Sc.
A signal Sf as shown in FIG. 3(e) is output. The serial/parallel conversion circuit 4j reads the signal Sf using a clock signal to obtain a received data signal Sg, as in the previous embodiment.

As described above, in this embodiment, the output of the buffer 4b, which is the transmission data signal, generates a reference voltage Vc that changes into two values depending on whether it is at a high level or a low level. The received data from the other party is determined by comparing the voltage of the transmission signal Sc with the voltage of the transmission signal Sc.

As a result, the same effect can be obtained with a simpler circuit than in the previous embodiment.

In each of the above embodiments, the clock signal output circuit 3 is arranged in one of the components, but it may be arranged independently of the two components communicating with each other, or it may be arranged in both parts and either one of them can be used arbitrarily. It may also be activated.

[Effects of the Invention] As described above, according to the present invention, data is transmitted and received using one signal line, and the output of the transmission data of the binary serial signal and the signal line are connected via a resistor. , When the output of the transmitted data is at high level or low level, the received data from the other party is determined by the voltage applied to the signal line, so the data sent from the other party at the same time as the data is transmitted. Since both parties can output data at arbitrary timing, there is no need to switch circuits or exchange control information between transmitting and receiving, which simplifies the circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a computer system according to an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of a data transmission/reception circuit, FIG. 3 is a time chart of each signal of the data transmission/reception circuit, and FIG. FIG. 5 is a circuit diagram showing another embodiment of the data transmitting/receiving circuit, and is a time chart of each signal of the data transmitting/receiving circuit. l...LSI, 2...IC, 3,6...data processing circuit, 4...data transmission/reception circuit, 4a...parallel/serial conversion circuit, 4b...buffer, 4d, 4
e...AND circuit, 4e. 4f, 41... Comparator, 'gAx+41... Reference voltage output circuit, 4h... OR circuit, 4j... Serial/parallel conversion circuit, 4k... Inverter, 5
...Clock signal output circuit, R, R1, R2, R3・
··resistance.

Claims (2)

[Claims] (1) In a data transmitting/receiving circuit that connects the two devices to be communicated with a signal line and transmits data using a serial signal, there is a signal line that connects both of the above and transmits and receives data with one wire, and a binary serial signal that transmits the transmitted data. a resistor inserted between the output of the data output means and the signal line; and a data output means that outputs data by comparing the voltage applied to the signal line with one reference voltage. a first received data discriminating means for discriminating received data from the other party when the output of the signal line is at a high level; and the data output means by comparing the voltage applied to the signal line with another reference voltage. a second received data discriminating means for discriminating received data from the other party when the output of is at a low level; and a data extracting means for selectively extracting received data from the first and second received data discriminating means. A data transmitting/receiving circuit characterized by: (2) In a data transmitting/receiving circuit that connects the two devices to be communicated with a signal line and transmits data using a serial signal, there is a signal line that connects both of the above and transmits and receives data with one wire, and a binary serial signal that transmits the transmitted data. a resistor inserted between the output of the data output means and the signal line, and a binary value depending on when the output of the data output means is at high level and when it is at low level. a reference voltage generating means for generating a changing reference voltage; a received data determining means for determining received data from a destination by comparing a voltage applied to the signal line with the reference voltage; and a received data discriminating means for determining received data from a destination. A data transmitting/receiving circuit comprising: data retrieval means for retrieving the data.