JPH04273151A - Manufacture of hybrid integrated circuit - Google Patents

Abstract

PURPOSE:To form a fine viahole in a fine land with high accuracy. CONSTITUTION:A viahole 32, which connects an outer lead pad (40) or a bonding pad (54) with a conducting passage (20), is formed by selectively removing a bonding agent layer (29) and an insulation resin layer (26) by means of an excimer laser with a viahole pattern formed before a circuit pattern is formed on an upper conducting layer as a mask and then plating (34) and (36) the whole surface of a conducting layer thereon. The viahole (32) is adapted to be formed at a position which precisely meets with the viahole pattern on the upper conducting layer and its size, and the viahole (32) and its lands (43) and (45) are formed by the same type of photo etching process, which makes it possible to form the viahole (32) and the lands (43) and (45) at the correct position. An integrated circuit device (59) is mounted directly on a conducting path 821) exposed by selectively removing the bonding agent layer (29) and the insulation resin layer (26) by the excimer laser.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a hybrid integrated circuit, and more particularly to a method for manufacturing a hybrid integrated circuit in which a multilayer circuit is formed on an insulated metal substrate.

0002

2. Description of the Related Art A conventional hybrid integrated circuit having a single conductive layer and a conventional hybrid integrated circuit having multiple conductive layers will be described with reference to FIGS. 11 and 12, respectively. Figure 11
1 is a plan view of a main part of a typical conventional hybrid integrated circuit having a single conductive layer; FIG. This kind of hybrid integrated circuit is 0.5mm
It has a three-layer structure consisting of an insulating metal substrate with a thickness of ~2 mm, an insulating resin layer with a thickness of 20 μm to 70 μm, and a conductive layer with a thickness of 35 μm to 70 μm.

[0003] The insulated metal substrate is made of aluminum whose surface is anodized in consideration of its heat dissipation properties and workability, and the insulated metal substrate is made of copper coated with a thermosetting resin having adhesive properties such as epoxy resin. The foil is applied using a hot press. This thermosetting resin becomes the above-mentioned insulating resin layer after thermosetting.

The copper foil is patterned in the order of 35 μm to 100 μm by a photoetching process, and as shown in FIG. 11, external lead pads (80) (82
), bus (84), bonding pad (86), jump pad (88) (92), die bond pad (94)
) (96), etc., is formed.

The die bond pad (94) of this conductive layer (
96) include chip-shaped microcomputers, programmable gate arrays, and other integrated circuit devices (100
)(102)(104) are fixed using a brazing material such as silver paste to form integrated circuit elements (100)(102)(1
The electrode 04) and a predetermined bonding pad (86) are connected by a bonding wire (110). In addition, irregularly shaped parts such as chip resistors and chip capacitors (106) (1
08) is soldered and fixed to a predetermined pad.

A conductive path for grounding the circuit extends from the external lead pad (80) for grounding to the entire area of the hybrid integrated circuit near the external lead pad (80) in consideration of current capacity and inductance. A large line width is formed, and a small line width is formed at the end. This ground conductive path inevitably intersects with the bus (84), and the locations thereof are jump-connected to each other by one to several bonding wires (110) depending on the current capacity. Further, at locations where it intersects with a large-capacity bus (84) and a single bonding wire connection is impossible, continuous jump connections are made via jump pads (88) and (92). In FIG. 12, this continuous jump connection is shown as an external lead pad (80) for grounding, a bonding wire (110), a jump pad (88), a bonding wire (110), a ground conductive path (90), and a ground conductive path. (90), bonding wire (110), jump pad (92), bonding wire (110)
, ground conductive path (91). Also, bus (
84) intersect with each other, discontinuously formed buses (
84) is connected with a large number of bonding wires (110),
You will be contacted.

FIG. 12 is a sectional view of a main part of a hybrid integrated circuit having multiple conductive layers. This type of hybrid integrated circuit was proposed in view of the fact that the number of bonding wires connected in the single conductive layer hybrid integrated circuit described above is enormous and that it is difficult to improve the degree of integration. , via holes (124) are formed at predetermined positions on a double-sided copper foil board with copper foil (122) pasted on both sides with an insulating resin layer (120) such as epoxy resin in between, and the entire surface is electroless copper plated (126). After electrically connecting both copper foils (122), photoetching is performed to form a circuit pattern in a predetermined shape. Usually, this hybrid integrated circuit is formed on another substrate with good heat dissipation properties in order to improve heat dissipation properties and mechanical strength. All of these hybrid integrated circuits are disclosed in detail in ``Latest Hybrid Mounting Technology'' published by Kogyo Research Institute Co., Ltd. on May 15, 1988.

[0008]

[Problems to be Solved by the Invention] Although the above-mentioned hybrid integrated circuit with a single conductive layer has excellent heat dissipation characteristics and mechanical strength, it is essential to have ground conductive paths (90) and (91) with a relatively large line width. There is a problem in that the degree of integration of the hybrid integrated circuit is reduced due to the area occupied by the conductive paths (90) and (91). In addition, since the ground conductive paths (90) and (91) always intersect with the address bus, data bus, and even control signal bus, it is impossible to form them continuously, and wire bonding is required at discontinuous locations. have. Another problem is that the degree of integration of the hybrid integrated circuit is reduced due to the area occupied by the pad for wire bonding.

Furthermore, ground conductive paths (90) (91)
jump pads (88) (92) because it is impossible to connect a single bonding wire where the wires intersect with large-capacity address buses and data buses and the wire span becomes long.
It is necessary to connect the continuous jump via the jump pad (
There is a problem that the degree of integration of the hybrid integrated circuit is reduced due to the occupied area of 88) and 92. Furthermore, at locations where the buses (84) intersect with each other, a large number of wire bondings are required to connect the discontinuously formed buses (84), and when the buses (84) are detoured to avoid wire bonding connections, There is a problem that the area occupied by the bus (84) increases and the degree of integration decreases. Furthermore, due to the above-mentioned problems, the pattern design of the conductive layer becomes complicated.

On the other hand, the above-described hybrid integrated circuit having multiple conductive layers has problems in terms of heat dissipation characteristics and mechanical strength. Moreover, in order to improve heat dissipation characteristics, even if a multilayer conductive layer is formed on another substrate with good heat dissipation characteristics, the conductive layer on which the chip can be mounted is thermally insulated by multiple insulating resin layers. Therefore, there is a problem that it is not possible to mount elements that generate high heat.

Furthermore, two conductive layers (1) of the double-sided conductive layer substrate
The epoxy resin used for the insulating resin layer (120) for adhering and insulating 22) is extremely difficult to chemically etch, and the formation of the via hole (124) is limited to mechanical means such as punching. are doing. As a result, the device that forms the via hole (124) and the device that forms the pattern of the conductive layer are different types of devices, and even if the processing accuracy of these devices is improved individually, the deviation between the via hole (124) and the pattern of the conductive layer will not occur. There are manufacturing problems that cannot be resolved.

Furthermore, the diameter of the via hole (124) formed by mechanical means is 2.
00 μm, and the land (12
8) has a problem in that the diameter reaches 300 μm. Therefore,
A hybrid integrated circuit that requires a large number of via holes (124) has a problem in that the degree of integration cannot be improved as much as expected even by multilayering the substrate. Note that if only polyimide resin is used for the insulating resin layer, chemical etching using the via hole pattern formed in the conductive layer as a mask is possible, but since the adhesiveness of polyimide resin is not good, the conductive layer (122 ) has a problem of peeling.

Therefore, the problem to be solved by the present invention is that when an epoxy resin with good adhesiveness is used as an insulating resin layer, or when an epoxy resin is used as an adhesive, the means for forming via holes are limited. result,
It is difficult to improve the positional accuracy of via holes, and it is difficult to improve the degree of integration of hybrid integrated circuits due to margin provision. Furthermore, when a multilayer conductive layer is formed on another substrate with good heat dissipation properties, the chip mounting surface is limited to the uppermost conductive layer, and the heat dissipation properties are not improved as much as expected.

[0014]

[Means for Solving the Problems] The present invention provides an insulator that sequentially forms via holes and chip mounting holes in the upper layer of copper foil of a two-layer copper foil board, and uses the via holes as a mask to bond and insulate both copper foils. The main feature is that the resin layer is excimer laser processed to form a via hole in the insulating resin layer, and the insulating resin layer below the chip mounting hole is further excimer laser processed to expose the underlying conductive layer.

[0015]

[Operation] To form via holes in the insulating resin layer that bonds and insulates both copper foils, excimer laser processing is used that uses the via holes formed in the copper foil as a mask, making it possible to create minute via holes that are close to the etching limit with high precision. can be formed into Further, since the via hole and its land are formed by the same type of process, no margin is required for the formation position. In addition, since the insulating resin layer under the chip mounting hole is subjected to excimer laser processing to expose the lower conductive layer, it is possible to mount the chip on any conductive layer, and the lower conductive layer can be removed after all circuit patterns are formed. Because of the exposure, etching of the underlying conductive layer is avoided during circuit pattern formation.

[0016]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 9. 9 is a plan view of a main part of a hybrid integrated circuit to which the present invention is applied, and FIG. 8 is a sectional view taken along the line A--A in FIG. 9. Referring to FIG. 1, the insulated metal substrate (10) has a thickness of 0.5 mm to 2.0 mm in consideration of heat dissipation characteristics and workability.
mm-thick aluminum (12) is used, and its surface is coated with an oxide film (14) with a thickness of 3 μm to 30 μm by anodic oxidation.
is formed. Further, this insulated metal substrate (10) has a size corresponding to a plurality of hybrid integrated circuits. 1st
The copper foil (16) is 35 μm thick, and a highly fluid A-stage epoxy resin is applied to its surface using a roller coater, and this epoxy resin is semi-cured to form the B-stage first adhesive. An agent layer (18) is formed.

In this step, the first copper foil (14) with the first adhesive layer (18) formed on the insulating metal substrate (10) is heated at a temperature of 130° C. to 150° C. in units of 150° C. using a hot press. It is thermocompressed at a pressure of 10Kg to 50Kg per square cm. The first adhesive layer (18) is completely cured by this thermocompression bonding process and has a thickness of about 20 μm. Then, the insulated metal substrate (10) is thermocompressed with the first adhesive layer (18).
) and the first copper foil (16) at a temperature of 130°C to 150°C for 5 to 10 hours to form the first adhesive layer (18).
After curing, it is sent to the next process.

Referring to FIG. 2, first, a first copper foil (1
6) Using a roller coater, coat the surface of photoresist (2).
4) and formed on the first copper foil (16), in addition to the ground conductive path (20) and the power conductive path (21), a bus connection conductive path (22) (this is indicated by a broken line in FIG. 10). The photoresist (24) on the photoresist (20) (20) (21) (22) is formed on the photoresist (24) by selectively exposing the photoresist (24) on the photoresist (24) and removing the selectively exposed portion with a solvent. be done. Mask alignment during this selective exposure can be performed with reference to the peripheral area of the insulated metal substrate (10).
It is also effective to punch predetermined positions of the insulated metal substrate (10) and the first copper foil (16) to form a pattern for mask alignment.

Next, using this photoresist (24) as a mask, the first copper foil (16) is selectively etched with a ferric chloride solution to form the ground conductive path shown in FIG. 2 on the first copper foil (10). (20), a power supply conductive path (21), and a bus connection conductive path (22) shown by a broken line in FIG. 10 are formed.

Referring to FIG. 3, a pattern is formed on the surface of the first conductive layer (16) (hereinafter, the patterned copper foil is referred to as a conductive layer) by selective etching of the first copper foil (16). An A-stage polyimide resin is applied using a roller coater, and this polyimide resin is completely cured to form a C-stage insulating resin layer (26) having a thickness of about 20 μm. The second copper foil (28) has a thickness of 35 μm, and an A-stage epoxy resin is applied to its surface using a roller coater, and this epoxy resin is semi-cured to form a B-stage second adhesive layer (29). ) is formed.

[0021] Then, a second adhesive layer (29
) and a second copper foil (28) is thermocompression bonded thereto. The second adhesive layer (29) is completely cured by this thermocompression bonding process and has a film thickness of 20 μm. Further, the previously completely cured insulating resin layer (26) functions to flatten the pattern surface of the first conductive layer (16) and improve the adhesion of the second copper foil (28). Functions to prevent poor insulation between the first conductive layer (16) and the second copper foil (28) due to outflow of the second adhesive layer (29)

Referring to FIG. 4, first, a second copper foil (2
8) Apply photoresist (30) to the surface, selectively expose the photoresist (30) on the via hole (32) and chip mounting hole (37) formed in the second copper foil (28), and A via hole (32) and a chip mounting hole (
37) is formed. In the example using a 35 μm thick copper foil, the pattern limit in the subsequent etching step is 35 μm, so the minimum diameter of the hole for the via hole (32) formed in the photoresist (30) is 35 μm.
It is μm.

During this selective exposure, the first conductive layer (
16), a ground conductive path (20) and a power conductive path (20) formed in
1) It is necessary to align the masks so that the via hole (32) is correctly formed on the bus connection conductive path (22) shown by the broken line in Figure 9, and refer again to the peripheral area of the insulated metal substrate (10). Mask alignment is performed by referring to a pattern for mask alignment formed by punching or punching from the back side of the insulated metal substrate (10).

Next, using the photoresist (30) as a mask, the second copper foil (28) is etched with a ferric chloride solution to form a via hole (32) and a chip mounting hole ( 37) is formed. At this time, a mask alignment pattern to be referred to in subsequent steps is also formed.

Note that the ground conductive path (20), power supply conductive path (21), and bus connection conductive path (22) of the first conductive layer (16)
) with a large line width allows relatively rough mask alignment, and even in that case, according to the invention, the degree of integration of the second conductive layer (28), which dominates the degree of integration of the hybrid integrated circuit, is impaired. It is important to note that This point will be discussed later.

Referring to FIG. 5, from above the via hole (32) pattern of the second copper foil (28), KrF, XeC
Excimer laser (
irradiate the entire surface of the copper foil (indicated by the arrow), and
8) via hole (32) and chip mounting hole (37)
) and the insulating resin layer (26) exposed by the second adhesive layer (29) are selectively removed one after another.

Excimer laser processing will now be explained with reference to FIG. In this Figure 10, the horizontal axis of the log scale is the energy density (Fluence mJ) of the excimer laser.
, the amount of processing per laser shot (Etch Depth μm) for each of polymer and metal is plotted on the vertical axis.

YAG, which has been conventionally used in industry,
In infrared laser processing using CO2 or the like, a thermal mechanism is used in which a laser beam is focused by a lens and the target to be processed in a high energy density region near the focal point is melted and vaporized. Therefore, infrared laser processing has the property that it does not select the material to be processed, and also has the property that continuous thermal influence on the periphery of the processing area is unavoidable.

On the other hand, in excimer laser processing, the excimer laser is irradiated onto the workpiece in a defocused state,
Machining is performed through an ablation process in which photons from an excimer laser chemically break molecular bonds on the surface to be processed. Therefore, excimer laser processing is non-thermal processing, and the energy density (threshold) at which the processing starts varies greatly depending on whether the object to be processed is a molecular bond or a metal bond. This threshold is approximately 100 mJ per square centimeter for all polymers and approximately 1 J per square centimeter for metals.
It is. In addition, since excimer laser processing is carried out using molecular chemistry, it has the characteristic that there is no heat influence or contamination around the processing area due to removed substances.

Referring again to FIG. 5, the second copper foil (28
) is irradiated with an excimer laser beam having an energy density of 100 mJ to 1 J per unit area, which is above the polymer threshold and below the metal threshold, the second copper foil (28 ) serves as a mask for the second adhesive layer (
29) and the insulating resin layer (26), the second copper foil (28
) via hole (32) and chip mounting hole (37)
Via holes (3
2) and a chip mounting hole (37) are formed, thereby exposing the power supply conductive path (21).

By this process characteristic of the present invention, the diameter of the via hole (32) can be reduced to the pattern limit of the second copper foil (28). In addition, a total of 4 in the example
A second adhesive layer (29) with a thickness of 0 μm and an insulating resin layer (
26) is completely removed by 200 shots of excimer laser at 500 mJ per square cm. Although the area around the via hole (32) of the second copper foil (28) is somewhat thermally affected by this excimer laser processing, the photoresist (30) protects the second copper foil (28). . The photoresist (30) is removed after this step.

Referring to FIG. 6, the second copper foil (28) surface, the via hole (32), the ground conductive path (20) exposed by the via hole (32), and the chip mounting hole (3
7) After activating this and the power supply conductive path (21) etc. exposed by the chip mounting hole (37), electroless plating is performed in a solution containing copper sulfate as the main component to coat the entire surface of them. The first plated copper layer (3
4) is formed. Then, this first plated copper layer (3
The second plated copper layer (
36) is formed to have a thickness of approximately 30 μm. This electrolytic plating complements electroless plating, which has a slow plating speed. In this step, as described above, the first and second plating layers (34) and (36) are formed on the entire surface, so the via hole (32) and the first copper foil (16) on which the chip is mounted are formed. becomes conductive unnecessarily.

Referring to FIG. 7, first, a photoresist (38) is applied to the surface of the second plated copper layer (36) using a roller coater, and selectively exposed to light to form the second plated copper layer (36).
36) External lead pads (40) and via holes (32) for grounding are added to the photoresist (38) applied to the surface.
) for land (43), wire bonding pad (54), address bus, data bus, etc. bus (55)
, a die bond pad (56), and other patterns corresponding to the circuit pattern are formed. In addition, in this process, as shown in FIG. )～(
52), patterns corresponding to all circuit patterns such as a grounded die bond pad (57) are formed. That is, in this step, the chip mounting hole (37) of the second copper foil (28) is
) is formed separately from the circuit pattern. More specifically, even if the first copper foil (16) and the via hole (32) are unnecessarily connected in the step of FIG. 6, they are separated during circuit pattern formation in this step.

Then, using this photoresist (38) as a mask, a second plated copper layer (36) is formed using a ferric chloride solution.
The first plated copper layer (34) and the second copper foil (28) are etched to form the second conductive layer of the circuit pattern shown in FIGS. 7 and 9.

Referring now to FIG. 9, the die bond pad (57) to be grounded is connected to a land (57) that is continuously formed thereon.
46), via hole (32), first conductive layer (16)
external lead pad (4) for grounding through the ground conductive path (20), land (43), and via hole (32).
0). Similarly, Rand (44) (45) (
47) is also connected to the external lead pad (40) for grounding. Also, the die bond pad (
56) is a land (49), a via hole (32), and a power supply conductive path (16) formed continuously thereon.
21), a land (48), and a via hole (32) to be connected to an external lead pad (41) that is connected to a power supply. Furthermore, buses that intersect with other buses (55) such as address buses include lands (51), (52), via holes (32), and bus connection conductive paths (
22).

In this embodiment, the pattern of the via hole (32) of the second copper foil (28) and its lands (43) to (
The patterns in 52) are individually formed by photo-etching twice, but their positions and sizes are uniquely determined only by the accuracy of the exposure equipment used in the photo-etching process, so the range of accuracy of the exposure equipment In this case, the pattern deviation between the via hole (32) and the lands (43) to (52) can be ignored. Therefore, the via hole (32
) when the diameter of the land (43) is designed to be 35 μm.
The minimum size of the short side of (52) is 105 μm, which is one third of the conventional land.

Referring to FIGS. 8 and 9, an integrated circuit element (58), such as a microcomputer, whose potential is the power supply potential of the element substrate, is fixed to the die bond pad (56) using a brazing material such as silver paste. , an integrated circuit element (such as a programmable gate array) whose substrate potential should be the power supply potential is similarly placed on the power supply conductive path (21) of the first conductive layer.
59), and attach an integrated circuit element (6) such as TTL to the die bond pad (57) whose element substrate potential should be grounded.
0) in the same manner, and after soldering irregularly shaped parts (61) (62) such as chip resistors and chip capacitors to predetermined pads, the integrated circuit elements (58) (59) (6
The electrode 0) and the wire bonding pad (54) are connected by a bonding wire (63) to complete the illustrated hybrid integrated circuit.

Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment.
By adjusting the beam diameter of the excimer laser beam that selectively removes the adhesive layer (29) and the insulating resin layer (26), the second
Connect the circuit pattern of the copper foil (28) to the via hole (32)
Changes can be made simultaneously with pattern formation. It is also possible to form the second plated copper layer (36) by nickel plating, or to further partially form a nickel plated layer on the second plated copper layer (36).

[0039]

[Effects of the Invention] As described above, according to the present invention, excimer laser processing is performed using a via hole pattern formed on a copper foil by photoetching as a mask, so that a via hole with a hole diameter up to the pattern limit of photoetching is formed. Therefore, high integration can be easily achieved. Also,
Since the via hole connecting both conductive layers is formed by a self-alignment method using excimer laser light, the position of the via hole and the conductive path connected to it is uniquely determined, and there is no need for a margin between them, resulting in a high Integration is achieved. Furthermore, since a multiphase conductive layer can be realized using copper foil on an insulated metal substrate, it is possible to provide a hybrid integrated circuit that has excellent electrical properties such as heat dissipation properties and noise resistance, and mechanical strength. Furthermore, since the chip mounting hole is simultaneously formed by excimer laser processing when the via hole is formed, the chip can be mounted on any conductive layer with excellent heat dissipation characteristics, and the process of forming the chip mounting hole is reduced.

[0041]

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a manufacturing process for explaining an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a manufacturing process for explaining one embodiment of the present invention.

FIG. 3 is a cross-sectional view of a manufacturing process for explaining one embodiment of the present invention.

FIG. 4 is a cross-sectional view of a manufacturing process for explaining one embodiment of the present invention.

FIG. 5 is a cross-sectional view of a manufacturing process for explaining one embodiment of the present invention.

FIG. 6 is a cross-sectional view of a manufacturing process for explaining one embodiment of the present invention.

FIG. 7 is a cross-sectional view of a manufacturing process for explaining one embodiment of the present invention.

FIG. 8 is a cross-sectional view of a manufacturing process for explaining one embodiment of the present invention.

FIG. 9 is a plan view of essential parts of a hybrid integrated circuit to which the present invention is applied.

FIG. 10 is a characteristic diagram illustrating processing characteristics of an excimer laser.

FIG. 11 is a plan view of a main part of a conventional single conductive layer hybrid integrated circuit.

FIG. 12 is a sectional view of a main part of a conventional multilayer conductive layer hybrid integrated circuit.

[Explanation of symbols]

10 Insulated metal substrate 16 First conductive layer 20 Ground conductive path 21 Power conduction path 22 Bus connection conductive path 28 Second conductive layer 32 Via Hall 36 Second plated copper layer 41 External lead pad 43 Land 54 Wire bonding pad 55 bus 56 Die bond pad 58 Integrated circuit element

Claims (7)

[Claims] 1. A step of adhering a first copper foil onto an insulating metal substrate via a first insulating resin layer, and selectively etching the first copper foil to form a circuit pattern on the first copper foil. and forming a second layer on the first copper foil via a second insulating resin layer.
a step of pasting a copper foil, a step of forming a via hole and a chip mounting hole in the second copper foil, and a step of attaching a second insulating resin using the via hole and chip mounting hole formed in the second copper foil as a mask. In the step of forming via holes and chip mounting holes in the second insulating resin layer by performing excimer laser processing on the layer, and in the via holes formed in the second copper foil and the second insulating resin layer, a step of electrically connecting a second copper foil; a step of selectively etching the second copper foil to form a circuit pattern on the second copper foil; and a step of forming a circuit pattern on the second copper foil under the chip mounting hole. A method for manufacturing a hybrid integrated circuit comprising the step of mounting an integrated circuit element directly on top of a circuit pattern. 2. The method of claim 1, wherein an image masked excimer laser is used to expose the first copper foil die bond pad. 3. In the via hole formed in the second copper foil and the second insulating resin layer by performing electroless plating on the second copper foil surface and the first copper foil surface exposed by the via hole. 2. The method of manufacturing a hybrid integrated circuit according to claim 1, further comprising electrically connecting the first and second copper foils. 4. After performing electroless plating on the second copper foil surface and the first copper foil surface exposed by the via hole,
4. The method of manufacturing a hybrid integrated circuit according to claim 3, further comprising electrolytically plating the plated surface. 5. Claim 1, wherein each of the steps is performed in units of circuit patterns of a plurality of hybrid integrated circuits.
A method for manufacturing a hybrid integrated circuit. 6. A first copper foil surface on which a circuit pattern is formed is coated with an insulating resin layer, and then a second copper foil is attached to this surface via a second insulating resin layer. 2. The method of manufacturing a hybrid integrated circuit according to claim 1. 7. The method of manufacturing a hybrid integrated circuit according to claim 1, wherein a chip-shaped circuit element is mounted on a circuit pattern formed by etching the first copper foil into a predetermined shape.