JPH0427714B2 - - Google Patents
Info
- Publication number
- JPH0427714B2 JPH0427714B2 JP58028514A JP2851483A JPH0427714B2 JP H0427714 B2 JPH0427714 B2 JP H0427714B2 JP 58028514 A JP58028514 A JP 58028514A JP 2851483 A JP2851483 A JP 2851483A JP H0427714 B2 JPH0427714 B2 JP H0427714B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor substrate
- floating gate
- silicon substrate
- high concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
Landscapes
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、浮遊ゲートと制御ゲートを有する不
揮発性半導体メモリ装置に係り、特に電気的に書
き換え可能なメモリ装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a control gate, and particularly to an electrically rewritable memory device.
浮遊ゲートを有する電気的に書き換え可能な不
揮発性メモリとして、例えば第１図に示すものが
知られている。第１図のａは平面図でありｂ，ｃ
はそれぞれａのＡ−A′，Ｂ−B′断面図である。
Ｐ型シリコン基板１１に形成されたn+層１２１，
１２２、これらのn+層１２１，１２２間に絶縁
膜を介して積層された浮遊ゲート１３制御ゲート
１４によりメモリトランジスタが構成されてい
る。またn+層１２２，１２３とこれらのn+層１
２２，１２３間に絶縁膜を介して形成されたゲー
ト電極１５により選択用トランジスタが構成され
ている。記憶内容の書き換えはn+層１２２と連
続的に形成されたn+層１２４上にトンネル電流
の流れうる薄い絶縁膜１６を介して浮遊ゲート１
３を延在させて、浮遊ゲート１３とn+層１２４
間の電荷の授受により行なわれる。１７はフイー
ルド絶縁膜である。
As an electrically rewritable nonvolatile memory having a floating gate, for example, the one shown in FIG. 1 is known. In Figure 1, a is a plan view, b, c
are AA' and BB' sectional views of a, respectively.
n + layer 121 formed on P-type silicon substrate 11,
122, a floating gate 13 and a control gate 14 stacked between these n + layers 121 and 122 with an insulating film interposed therebetween constitute a memory transistor. Also, the n + layers 122 and 123 and these n + layers 1
A selection transistor is constituted by a gate electrode 15 formed between 22 and 123 with an insulating film interposed therebetween. Memory contents are rewritten via the floating gate 1 via a thin insulating film 16 through which a tunnel current can flow on the n + layer 124 formed continuously with the n + layer 122.
3, floating gate 13 and n + layer 124
This is done by transferring charges between the two. 17 is a field insulating film.
この様な構造のメモリトランジスタにおいて
は、通常の書き込み条件（プログラム電圧（パル
ス）VPP＝20V、10ms）によつて記憶内容を書き
換えるには、トンネル絶縁膜１６の厚さを〜120
〓程度に薄くする必要があり、素子形成方法及
び、記憶内容と保持を保障する上で問題点があつ
た。即ち、前記書き込み条件で記憶内容の書き換
えが可能であれば、トンネル絶縁膜１６の厚さは
厚い方が望ましい。 In a memory transistor with such a structure, in order to rewrite the memory contents under normal write conditions (program voltage (pulse) V PP = 20 V, 10 ms), the thickness of the tunnel insulating film 16 must be ~120 mm.
It was necessary to make the device as thin as 0.000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, That is, if the stored contents can be rewritten under the above write conditions, it is desirable that the tunnel insulating film 16 be thicker.
本発明は上記の点に鑑みなされたもので、トン
ネル絶縁膜厚を厚く保ちながら、通常の書き込み
条件で書き換え可能な記憶素子を提供する事を目
的としている。
The present invention has been made in view of the above points, and an object of the present invention is to provide a memory element that can be rewritten under normal write conditions while maintaining a thick tunnel insulating film.
本発明では第２図に示す如く、トンネル絶縁膜
１６を介して凸型に形成されたシリコン基板１１
と浮遊ゲート１３が対向におり浮遊ゲート１３は
凸型シリコン基板端部を被う如く対向させる事に
より端部での電界集中を起こし、厚いトンネル絶
縁膜１６を用いた場合においても、通常の書き込
み条件で書き換えの行える記憶素子を実現してい
る。尚、第２図ａ，ｂは、第１図ａに平面図で示
された記憶素子において、本発明を用いた場合に
ついてそれぞれＡ−A′，Ｂ−B′断面図を示して
いる。
In the present invention, as shown in FIG. 2, a silicon substrate 11 formed in a convex shape with a tunnel insulating film 16
The floating gates 13 face each other so as to cover the edges of the convex silicon substrate, thereby causing electric field concentration at the edges. Even when a thick tunnel insulating film 16 is used, normal writing This realizes a memory element that can be rewritten under certain conditions. Note that FIGS. 2a and 2b show cross-sectional views taken along line A-A' and line B-B', respectively, in the case where the present invention is used in the memory element shown in plan view in FIG. 1a.
本発明によれば、トンネル絶縁膜の厚さを厚く
する事ができるため、素子製造が容易となり素子
製造の歩留りが向上する。また、厚い絶縁膜で浮
遊ゲートが被われるため、記憶情報の保持特性が
良好であり、信頼性の高い素子が実現できる。
According to the present invention, since the thickness of the tunnel insulating film can be increased, device manufacturing is facilitated and the yield of device manufacturing is improved. Furthermore, since the floating gate is covered with a thick insulating film, the retention characteristics of stored information are good, and a highly reliable device can be realized.
次に、本発明を実施例を用いて説明する。第３
図ａに示す如く、Ｐ型シリコン基板１１上に凸部
形成のためのマスク材１２を所望の形状に残置し
た後、シリコン基板１１を除去し、凸部を形成す
る。次に、形成された凹部に酸化膜１３をシリコ
ン基板１１の表面に一致する如く埋め込むｂ。次
に、ｃに示す如くシリコン基板１１の凸部と埋め
込まれた酸化膜１３の一部を含む領域以外を被う
マスク材１４を残置しシリコン基板１１内のn+
層１５の形成及び酸化膜１３の一部除去を行いシ
リコン基板１１の凸部表面より酸化膜表面を後退
させる。次に、ｄに示す如く、シリコン基板１１
の凸部にトンネル酸化膜１６を例えば200〓成長
させ多結晶ケイ素より成る浮遊ゲート１７を形成
し、以降は公知の如く、制御ゲートを積層し、素
子を形成する。尚、本実施例では第３図ｂの工程
で凹部への酸化膜の埋め込みをSi基板表面にまで
一致する如く行う場合について説明したが、埋め
込みを途中まで行つても同様の効果を得る事がで
きる。
Next, the present invention will be explained using examples. Third
As shown in FIG. 1A, a mask material 12 for forming a convex portion is left on a P-type silicon substrate 11 in a desired shape, and then the silicon substrate 11 is removed to form a convex portion. Next, an oxide film 13 is buried in the formed recess so as to match the surface of the silicon substrate 11 b. Next, as shown in c, a mask material 14 is left to cover the area other than the convex portion of the silicon substrate 11 and a part of the buried oxide film 13, and the n +
The layer 15 is formed and a portion of the oxide film 13 is removed, and the surface of the oxide film is set back from the surface of the convex portion of the silicon substrate 11. Next, as shown in d, the silicon substrate 11
For example, a tunnel oxide film 16 of 200 mm is grown on the convex portion to form a floating gate 17 made of polycrystalline silicon, and thereafter control gates are laminated in a known manner to form an element. In this example, the case where the oxide film is buried in the recessed portion in the step shown in FIG. can.
第１図ａは従来例を説明するための平面図、
ｂ，ｃはその断面図、第２図ａ，ｂは本発明を説
明するための断面図、第３図ａ〜ｄは本発明の一
実施例を示す断面図である。
FIG. 1a is a plan view for explaining a conventional example;
b and c are cross-sectional views thereof, FIGS. 2 a and b are cross-sectional views for explaining the present invention, and FIGS. 3 a to 3 d are cross-sectional views showing one embodiment of the present invention.
Claims (1)
換え可能な不揮発性メモリ装置において、前記浮
遊ゲートへの電荷の授受は、半導体基板表面に形
成された前記半導体基板と逆電導型の高濃度不純
物領域との間でトンネル電流の流れうる薄い絶縁
膜を介して行なわれ、かつ前記高濃度不純物領域
は半導体基板上に形成された凸型領域表面に形成
されており、前記半導体基板の凸型領域の他の部
分は凸型領域表面が突出する如く、絶縁膜によつ
て埋められる如く形成されている事を特徴とする
不揮発性半導体記憶装置。1. In an electrically rewritable nonvolatile memory device having a floating gate and a control gate, charge is transferred to and from the floating gate between the semiconductor substrate and a high concentration impurity region of opposite conductivity type formed on the surface of the semiconductor substrate. The high concentration impurity region is formed on the surface of a convex region formed on the semiconductor substrate, and the high concentration impurity region is formed on the surface of the convex region formed on the semiconductor substrate. 1. A nonvolatile semiconductor memory device characterized in that a portion is formed so that the surface of a convex region protrudes and is filled with an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58028514A JPS59155172A (en) | 1983-02-24 | 1983-02-24 | Nonvolatile semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58028514A JPS59155172A (en) | 1983-02-24 | 1983-02-24 | Nonvolatile semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59155172A JPS59155172A (en) | 1984-09-04 |
| JPH0427714B2 true JPH0427714B2 (en) | 1992-05-12 |
Family
ID=12250788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58028514A Granted JPS59155172A (en) | 1983-02-24 | 1983-02-24 | Nonvolatile semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59155172A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3710880B2 (en) * | 1996-06-28 | 2005-10-26 | 株式会社東芝 | Nonvolatile semiconductor memory device |
-
1983
- 1983-02-24 JP JP58028514A patent/JPS59155172A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59155172A (en) | 1984-09-04 |
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