JPH0427728B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a flip-flop circuit with preset or clear function suitable for MOS integrated circuit implementation. The applicant has proposed the J-K flip-flop circuit shown in FIG. 1 as a J-K flip-flop circuit that can determine the level of the output Q using the preset and clear inputs without being affected by the J input, K input, or clock signals. (Patent Application No. 113341, 1983). Now let's consider a case where a preset is applied to this flip-flop.
If neither preset nor clear is applied, use Preset=
“1”, Clere = “1”, so apply the preset
If Preset="0", the output of the inverter 1 will be "1", the output of the NOR gate 2 will be "0", and therefore the output Q will be "1". On the other hand, since the output of inverter 3 is "0", the output Q _M of NAND gate 4 is "1", and the clear input Clear is "1", so the output of inverter 5 is "0", and the output of inverter 6 is "0". It is “1”. Further, the output of the OR gate 7 becomes "1" because the output of the inverter 1 is "1", and as a result, all the inputs of the NAND gate 8 become "1", so the output _M becomes "0". As a result, the output of AND gate 9 is “0”
In the end, all the inputs of the NOR gate 10 become "0", so its output Q _S becomes "1", and therefore the output becomes "0". When presetting is applied in this way, in order to determine Q = 1, three stages of gates are required: inverter 1, NOR gate 2, and inverter 11, but in order to determine output = 0, inverters 1, 3, NAND gate 4, 8. Noah Gate 10
(including the AND gate 9), six stages of gates of the inverter 12 are required. Furthermore, as can be seen from the gates 1 to 17, the upper and lower sides of the circuit shown in FIG. 1 have a symmetrical structure, so that when clearing is applied, the same thing can be said as when applying preset. When counting the number of gate stages, for example, including the AND gate 9 at the front stage and the NOR gate 10 at the rear stage
is counted as one stage, which is correct in integrated circuits. This is because, in an integrated circuit, one stage is defined as one path from a power source (for example, ground) to an output (for example, the output of gate 10). Therefore, if you draw gates 9 and 10 in an actual wiring diagram, the distance from the power supply of these two gate circuits to the output of gate 10 is 1.
This results in a pass, and gates 9 and 10 become indivisible functions, so both of them count as one stage of gates. The same can be said about the method of counting the number of gate stages, which will be described later. As mentioned above, for both preset and clear signals to be input and the output Q or to be determined, the response time is equivalent to three gate stages, but for the negative phase output or Q, the response time is equivalent to six gate stages. After all, this response time becomes the response time when presetting or clearing is applied when the circuit shown in FIG. 1 is used. On the other hand, considering the response time of the circuit shown in Figure 1 to the clock input Clock, this circuit is active at "1" in response to the clock input, so the response time of the output terminal _{Q is} = 0, the response time of two stages of gates, NOR gate 2 and inverter 11, or NOR gate 10 and inverter 12, is sufficient. By the way, integrated circuits are currently aiming for high-speed operation and low power consumption, and even if the switching speed of the MOS transistors that make up the circuit shown in Fig. 1 is increased, the output Q will not be fixed as described above. If there is a difference in the number of gate stages between the two, speeding up the system for presetting or clearing has been hindered. Furthermore, when this system is configured with single-channel MOS transistors, there is a period during which these outputs are at the same level until both outputs Q, are reliably determined, and a DC path is created in the output section during that period. , a wasteful amount of current was consumed. The present invention was made in view of the above circumstances, and enables high-speed operation and low power consumption by reducing the difference in response time until the level of each output terminal is determined when presetting or clearing is applied. The purpose of this invention is to provide a flip-flop circuit. An embodiment of the present invention will be described below with reference to FIG. Note that this embodiment structurally corresponds to that of FIG. 1, so the same reference numerals are used for corresponding parts. As shown in FIG. 2, input J is connected to one input terminal of OR gate 14 via inverter 15, and input K is connected to one input terminal of OR gate 7 via inverter 16. clock input
Clock is connected to OR gate 1 via inverter 17
Connected to one input terminal of 4 and 7, preset input
Preset is connected to one input terminal of OR gate 7 via inverter 1, and clear input Clear is connected to one input terminal of OR gate 14 via inverter 5. The output terminal of OR gate 14 is NAND gate 4
The output terminal of the OR gate 7 is connected to the input terminal of the NAND gate 8. The output terminal of the NAND gate 4 is connected to one input terminal of the AND gate 13 and one input terminal of the NAND gate 8, and the output terminal of the NAND gate 8 is connected to one input terminal of the AND gate 9 and one input terminal of the NAND gate 4. The output terminal of inverter 17 is connected to one input terminal of AND gates 13 and 9, the output terminal of inverter 5 is connected to one input terminal of NAND gate 8 via inverter 6, and the output terminal of inverter 1 is connected to one input terminal of NAND gate 8 via inverter 3. and is connected to one input terminal of the NAND gate 4.
The output terminal of AND gate 13 is one input terminal of NOR gate 2, and the output terminal of AND gate 9 is one input terminal of NOR gate 1.
Connected to one input terminal of 0. The output terminal of the inverter 1 is connected to one input terminal of the NOR gate 2, and the output terminal of the NOR gate 10 is connected to the other input terminal. The output terminal of the inverter 5 is connected to one input terminal of the NOR gate 10, and the output terminal of the NOR gate 2 is connected to the other input terminal. In this circuit of FIG. 2, NAND gate 4,
8 and OR gates 7 and 14 constitute a master flip-flop circuit 19, and NOR gates 2 and 10 and AND gates 9 and 13 constitute a slave flip-flop circuit 20. Further, in the circuit shown in FIG. 2, preset and clear are applied to an output logic circuit provided at the output stage of the slave flip-flop 20 and consisting of NOR gates 21 and 22. That is, one input terminal of this NOR gate 21 is connected to the output terminal of NOR gate 2,
The other input terminal is connected to the output terminal of the inverter 5. Further, one input terminal of the NOR gate 22 is connected to the output terminal of the NOR gate 10, and the other input terminal is connected to the output terminal of the inverter 1. Note that the illustration of the circuit 18 corresponds to the circuit 18 in FIG. That is, the output terminal of the inverter 1 in FIG. The input terminal of NOR gate 2 is connected to the output terminal of AND gate 13,
The input terminal of NOR gate 10 is connected to the output terminal of AND gate 9, the output terminal of NOR gate 2 is connected to the input terminal of OR gate 7, and the output terminal of inverter 6 is connected to NAND gate 8.
The input terminal of the inverter 5 is connected to the input terminal of the OR gate 14, and the output terminal of the inverter 5 is connected to the input terminal of the OR gate . When a preset is applied to the above master-slave flip-flop, the preset input Preset=
0, clear input Clear=1, so inverter 1
The output of the NOR gate 2 is "1", so the output of the NOR gate 2 is "0". Further, since the output of the inverter 5 is "0", the output Q is set to "1". on the other hand,
Since the output of inverter 1 is “1”, the NOR gate 2
The output of 2 is set to "0". In this way, in the circuit shown in FIG. 2, the output level is determined by the three stages of the inverter 1 and the NOR gates 2 and 21 on the output Q side, and the output level is determined by the two stages of the inverter 1 and the NOR gate 22 on the output side. Moreover, the difference in the number of stages between both outputs is only one stage. Therefore, compared to the circuit shown in Fig. 1, the circuit shown in Fig. 2 requires fewer gate stages from applying the preset to determining the output Q, and the difference in the number of gate stages between Q is only one stage. Therefore, each MOS that makes up the circuit in Figure 2
By increasing the switching speed of transistors, response time can be significantly reduced. Furthermore, since the difference in response time between the outputs Q and the outputs Q is small, it is possible to reduce the wasted current that would be generated when the outputs Q are at the same level, and thus it is possible to reduce power consumption. Furthermore, since the circuit shown in Figure 2 has a symmetrical structure between the upper and lower sides, that is, the preset input supply line and the clear input supply line, the same thing can be said when clearing is applied as when applying preset. It is. The table shown below is a truth table that summarizes the operation of the flip-flop circuit shown in Figure 2.
The figure shows a specific example of a circuit in which the circuit of FIG. 2 is implemented using a CMOS (complementary MOS) circuit.

[Table] Note that the present invention is not limited to the embodiments, but can be applied to various types of flip-flops, for example, if "1" is supplied to both J and K inputs, it becomes a binary flip-flop. Yes, again
It is applicable not only to CMOS type but also to various types such as single channel type MOS. Further, in the embodiment, the configuration is such that both preset and clear are applied, but only one of them may be applied. As explained above, according to the present invention, it is possible to reduce the response time until the level of each output terminal is determined when presetting or clearing is applied, and the difference therebetween, thereby creating a flip-flop circuit capable of high-speed operation and low power consumption. It is something that can be provided.

[Brief explanation of drawings]

Fig. 1 is a master-slave flip-flop circuit diagram, Fig. 2 is a circuit diagram of an embodiment of the present invention, and Fig. 3 is a circuit diagram of an embodiment of the present invention.
The figure is a circuit diagram showing a specific example of FIG. 2. 1, 3, 5, 6...Inverter, 2, 10, 2
1, 22... Noah Gate, 4, 8... Nand Gate,
7,14...OR gate, 9,13...AND gate, 19...master flip-flop, 20...slave flip-flop.

Claims (1)

[Claims] 1. The input/output terminals of the first inverting logic gate 4 and the input/output terminals of the second inverting logic gate 8 are connected to each other, and one input terminal of the first and second inverting logic gates is connected to each other. A master flip-flop has a first non-inverting logic gate 14 and a second non-inverting logic gate 7 connected in cascade, an input/output terminal of the third inverting logic gate 2 and an input/output terminal of the fourth inverting logic gate 10, respectively. The output terminals of the third non-inverting logic gate 13 and the fourth non-inverting logic gate are connected to one input terminal of the third and fourth inverting logic gates, respectively.
a slave flip-flop in which non-inverting logic gates 9 are connected in cascade and output terminals of the first and second inverting logic gates are connected to one input terminal of the third and fourth non-inverting logic gates, respectively; a fifth inverting logic gate 21 cascade-connected to the output of the third inverting logic gate; a sixth inverting logic gate 22 cascade-connecting the output of the fourth inverting logic gate; and the output of the slave flip-flop via the fifth inverting logic gate, and the sixth inverting logic gate. 1. A JK type flip-flop circuit comprising a control signal supply line for setting an inverted output of a slave flip-flop via a logic gate. 2 The input/output terminals of the first inverting logic gate 4 and the input/output terminals of the second inverting logic gate 8 are connected to each other, and a first non-inverting logic gate is connected to one input terminal of the first and second inverting logic gates, respectively. A master flip-flop in which a logic gate 14 and a second non-inverting logic gate 7 are connected in cascade, an input/output terminal of the third inverting logic gate 2, and an input/output terminal of the fourth inverting logic gate 10 are connected to each other. A third non-inverting logic gate 13 and a fourth non-inverting logic gate are connected to one input terminal of the third and fourth inverting logic gates, respectively.
a slave flip-flop in which non-inverting logic gates 9 are connected in cascade and output terminals of the first and second inverting logic gates are connected to one input terminal of the third and fourth non-inverting logic gates, respectively; a fifth inverting logic gate 21 cascade-connected to the output of the third inverting logic gate; a sixth inverting logic gate 22 cascade-connecting the output of the fourth inverting logic gate; and the output of the slave flip-flop via the fifth inverting logic gate, and the sixth inverting logic gate. a preset input supply line that sets the inverting output of the slave flip-flop through the logic gate, and a clear input to the other inputs of the fourth inverting logic gate and the fifth inverting logic gate; J- characterized in that it comprises a clear input supply line for setting the output of the slave flip-flop via a logic gate and the inverted output of the slave flip-flop via a sixth inverting logic gate.
K-type flip-flop circuit.