JPH04280384A - Operating mode designating system - Google Patents

Abstract

PURPOSE:To use in common an input terminal for both a normal mode and a test mode and to reduce the number of pins by fixing the level of a system clock input terminal, and using this level as a mode switching signal for announcing the start of the test mode. CONSTITUTION:Signals S1 and S2 are inputted from pins 1 and 2. In the normal mode, the signal S1 is a system clock signal CK. In the test mode, this signal is the signal of logic '1'. A delay circuit 3 delays the input signal S1 of the pin 1 only for the half cycle of the system clock signal CK. The output terminal of the delay circuit 3 is connected to one input terminal of an AND circuit 4. The output terminal of the AND circuit 4 is connected to the input terminal of a delay circuit 5 and one input terminal of an AND circuit 6. When the system clock signal is supplied to a terminal C, a synchronous order circuit 8 is turned to the normal mode and when the signal from the pin 2 is supplied, this circuit 8 is turned to the test mode.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for specifying an operating mode in an LSI without providing a special pin for a signal for switching the operating mode.

0002

2. Description of the Related Art Recently, as LSI circuits have become more complex, the need for additional terminals (or pins) has increased, and there is a trend toward increasing the number of pins. However, since there are restrictions on the number of pins due to the physical size of the LSI, one of the important design issues is how to reduce the number of pins to realize a desired LSI circuit. Conventionally, as a method for switching the operation of an LSI between a normal mode and a test mode, a special mode switching terminal (pin) is provided for externally supplying a mode switching signal. FIG. 3 shows such a conventional example.

In FIG. 3, 11, 12 and 13 are L
Input terminals (pins) provided on SI are shown. A system clock signal CK is input from pin 11. A mode switching signal SW is input from pin 12. Pin 13 inputs signal S. The synchronous sequential circuit 15 operates according to the system clock signal CK in the normal mode, and operates according to the signal S in the test mode. The other circuit 16 is
It is a circuit of a different system from the synchronous sequential circuit 15, and operates by inputting the signal S. Input terminals A and M of mode switching circuit 14
and B are connected to pins 11, 12 and 13, respectively, and the output terminal X is connected to a synchronous sequential circuit 15.

The mode switching circuit 14 outputs the clock signal CK input to the A terminal from the output terminal X when the mode switching signal SW input to the M terminal is a signal indicating the normal mode, for example, logic 1 (“H”). is output to the synchronous sequential circuit 15, and when the mode switching signal SW is a signal indicating the test mode, for example, logic 0 (“L”), the signal S input to the B terminal is output from the output terminal X to the synchronous sequential circuit. Output to 15. As mentioned above, the operation mode of the synchronous sequential circuit 15 is switched between the normal mode and the test mode depending on the level of the mode switching signal SW input from the pin 12, and the mode switching operation is performed frequently. Therefore, the usage efficiency of pin 12 is lower than that of other pins.

[0005]

[Problem to be Solved by the Invention] As LSI circuits become more complex and have more pins, independent pins are assigned to input/output signals of high importance, and signals of relatively low importance, such as those shown in FIG. 3, are assigned independent pins. It is required that pins such as pin 12, which have low usage efficiency, be provided as little as possible by devising a circuit configuration. The present invention, in response to the above requirements,
An object of the present invention is to provide an operation mode designation method that enables switching of the operation mode of a circuit without providing an operation mode switching terminal.

[0006]

[Means for Solving the Problems] The operation mode designation method according to the present invention changes the operation of an internal circuit to a first signal by inputting a second signal to a terminal to which a first signal is normally input in an LSI. mode to a second mode. The first signal is the system clock, the second
The signal is held at logic 1 or logic 0. Specifically, the operation mode designation method according to the present invention is based on the LS
In I, the internal circuit operates in normal mode by the system clock signal and operates in test mode by other signals, and when the system clock signal is input to the system clock input terminal, the system clock signal is supplied to the internal circuit. and means for operating in the test mode by supplying other signals to the internal circuit when a mode switching signal held at logic 1 or logic 0 is input to the system clock input terminal while operating in the normal mode. be done.

[0007]

[Operation] With the above configuration, the internal circuit of the LSI is normally activated by the first signal, for example, the system clock signal.
operating in the operating mode. At this time, by inputting a second signal, that is, a mode switching signal, instead of the system clock signal to the system clock input terminal, the internal circuit is shifted to the second operation mode, for example, the test mode. In test mode, the internal circuit operates by inputting other signals. As mentioned above, when the internal circuit of an LSI normally operates with a system clock signal and operates with other signals in test mode, the level of the system clock input terminal is fixed to logic 1 or logic 0. , this is used as a mode switching signal to notify that test mode has been entered. Therefore, the system clock input terminal can be used for both the normal mode and the test mode, and there is no need to provide a special terminal for mode switching.

[0008]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the operation mode designation method according to the present invention. In FIG. 1, 1 and 2 indicate input terminals (pins) of the LSI. Signals S1 and S2 are input from pins 1 and 2, respectively. The signal S1 is the system clock signal CK in the normal mode, and is a logic 1 (“H”) signal in the test mode. Signal S2 is a signal unrelated to signal S1. Delay circuit 3 delays input signal S1 at pin 1 by approximately half a cycle of system clock signal CK. The output terminal of the delay circuit 4 is connected to one input terminal of the AND circuit 4. The other input terminal of AND circuit 4 is connected to pin 1.

The output terminal of the AND circuit 4 is connected to the input terminal of the delay circuit 5 and one input terminal of the AND circuit 6. The output terminal of the delay circuit 5 is connected to the other input terminal of the AND circuit 6. The selector 7 has input terminals A, B and SEL, and an output terminal X. When the input signal of the SEL terminal is "L", the input signal of the A terminal is output from the X terminal, and the input signal of the SEL terminal is " It has a function of outputting the input signal of the B terminal from the X terminal when it is "H".

Input terminals A, B and SEL of selector 7
are connected to pin 1, pin 2, and the output terminal of the AND circuit 6, respectively, and the output terminal X is connected to the clock terminal C of the synchronous sequential circuit 8. When the system clock signal CK is supplied to the terminal C, the synchronous sequential circuit 8 enters the normal mode and performs normal operations. When testing the synchronous sequential circuit 8, terminal C supplies the signal S2 from pin 2. At this time, the synchronous sequential circuit 8 enters the test mode. The other circuit 9 is connected to pin 2 and operates normally with signal S2.

The operation of the circuit shown in FIG. 1 will be explained below. FIG. 2 is a time chart showing the relationship of signals in each part of the circuit shown in FIG. In Figure 2, (1), (2), (3
), (4), (5), (6), (7), and (8) are the input signal S1 of pin 1, the input signal S2 of pin 2, the output signal S3 of delay circuit 3, and the AND circuit, respectively. 4, an output signal S5 of the delay circuit 5, an output signal S6 of the AND circuit 6, an output signal S7 of the selector 7, and time t.

First, in the normal mode, the input signal S1 at pin 1 is the system clock signal CK with period T. It is assumed that the delay circuit 3 delays the input signal S1 by approximately half the period of the system clock signal CK ((T/2)+ΔT1). The AND of the signal S3 given such a delay and the original signal S1 is as shown in (4) in FIG. If the delay circuit 3 provides an accurate delay of T/2, the signal S4 becomes an "L" signal. If the delay time given to the input signal by the delay circuit 5 is ΔT2, the delayed output signal S5 will be as shown in (5) in FIG. Therefore, the output signal S6 of the AND circuit 6 is S4
and S5, and is always "L" while the system clock signal CK is input, that is, during normal mode.
become. During this time, since the "L" signal is supplied to the SEL terminal of the selector 7, the selector 7 selects the terminal A, and therefore the signal S1, that is, the system clock signal CK is supplied to the synchronous sequential circuit 8.

Next, at time t2, in order to enter the test mode, the input signal S1 at pin 1 is set to an "H" signal held at logic 1. The output signal S3 of the delay circuit 3 is (
At time t3, which is delayed by T/2)+ΔT1, the signal becomes an "H" signal, and at the same time, the signal S4 also becomes an "H" signal. Further delayed by ΔT2, at time t4, the signal S5 becomes an "H" signal, and at the same time, the mode selection signal S6 changes from an "L" signal to an "H" signal. Therefore, selector 7 switches the input terminal from A to B,
As a result, the signal S2 from pin 2 is sent to the synchronous sequential circuit 8.

As described above, when the input signal S1 is the system clock CK, the synchronous sequential circuit 8 inputs this system clock and performs normal operation, and when the input signal S1 is held at logic 1, it performs a test operation. mode and is tested by the input signal S2 of the extraneous circuit 9. In addition,
By reversing the input terminals A and B of the selector 7, the test mode can be set when the input signal S1 is held at logic 0.

[0015]

According to the present invention, there is no need to provide a special terminal (pin) for specifying the operation mode of an LSI circuit, and it is possible to cope with an increase in the number of pins of an LSI.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a time chart of signals in the circuit of FIG. 1;

FIG. 3 is a diagram for explaining a conventional technique.

[Explanation of symbols]

1, 2 Pins 3, 5 Delay circuits 4, 6 AND circuit 7 Selector 8 Synchronous sequential circuit 9 Other circuits 11, 12, 13 Pin 14 Mode switching circuit 15 Synchronous sequential circuit 16 Other circuits S1, S2, S3, S4, S5, S6, S7CK, S,
SW signal

Claims (5)

[Claims] [Claim 1] In an LSI, the operation of the internal circuit is shifted from the first mode to the second mode by inputting a second signal to a terminal to which the first signal is normally input. Operation mode specification method. 2. The operation mode designation method according to claim 1, wherein the first signal is a system clock, and the second signal is a signal held at logic 1. 3. The operating mode designation system according to claim 1, wherein the first signal is a system clock and the second signal is a signal held at logic 0. 4. In an LSI, when the system clock signal is input to the system clock input terminal, the internal circuit operates in the normal mode by the system clock signal and in the test mode by other signals, and when the system clock signal is input to the system clock input terminal. and means for supplying the internal circuit with the other signal to cause the internal circuit to operate in a normal mode and, when a mode switching signal is input to the system clock input terminal, to supply the other signal to the internal circuit to cause the internal circuit to operate in a test mode. An operation mode specification method characterized by: 5. The mode designation method according to claim 4, wherein the mode switching signal is a signal held at logic 1.