JPH04280443A - Interconnection of electric parts on substrate - Google Patents
Interconnection of electric parts on substrateInfo
- Publication number
- JPH04280443A JPH04280443A JP3272090A JP27209091A JPH04280443A JP H04280443 A JPH04280443 A JP H04280443A JP 3272090 A JP3272090 A JP 3272090A JP 27209091 A JP27209091 A JP 27209091A JP H04280443 A JPH04280443 A JP H04280443A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive material
- substrate
- fluxing agent
- solder
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
- H05K3/305—Affixing by adhesive
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/36—Selection of non-metallic compositions, e.g. coatings or fluxes; Selection of soldering or welding materials, conjoint with selection of non-metallic compositions, both selections being of interest
- B23K35/3612—Selection of non-metallic compositions, e.g. coatings or fluxes; Selection of soldering or welding materials, conjoint with selection of non-metallic compositions, both selections being of interest with organic compounds as principal constituents
- B23K35/3613—Polymers, e.g. resins
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0145—Polyester, e.g. polyethylene terephthalate [PET], polyethylene naphthalate [PEN]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3489—Composition of fluxes; Application thereof; Other processes of activating the contact surfaces
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/853—On the same surface
- H10W72/856—Bump connectors and die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】この発明は一般的には電子回路に
関し、かつより特定的には電気的相互接続方法に関し、
そしてさらに特定的には集積回路のフリップチップ取り
付けおよび封入に関する。TECHNICAL FIELD This invention relates generally to electronic circuits and more particularly to electrical interconnection methods.
and more particularly relates to flip chip mounting and encapsulation of integrated circuits.
【0002】0002
【従来の技術】人手によるワイヤボンディングの高価格
性、信頼性のなさ、および低い生産性を除去するために
はんだバンプ(solder bump)相互接続が
開発された。フリップチップ集積回路のためのはんだバ
ンプ相互接続技術は何らかの形でおよそ20年間使用さ
れてきた。初期の、複雑性の少ない集積回路は典型的に
は周辺の接続部を有するのに反して、フリップチップバ
ンピング技術はそれが全領域のアレイに進むに連れて相
互接続密度のかなりの増大を許容した。制御された崩壊
(コラプス:collapse)チップ接続はダイ上の
ウエット可能な金属端子上に被着されたはんだバンプお
よび基板上のはんだによるウエット可能な端子の整合す
るフットプリントを使用する。上下逆の集積回路(フリ
ップチップ)が基板に対し整列されかつすべての接合が
同時にはんだをリフローすることにより形成される。制
御されたコラプス方法においては、はんだのバンプが集
積回路の端子上に被着され、かつ該はんだバンプが厚膜
ガラスのダムを用いることにより端子から流れ出すこと
が抑制され、基板のメタリゼーションの先端へのはんだ
の流れが制限される。同様に、集積回路上のはんだの流
れが該集積回路上の化学的に蒸着されたガラスのパッシ
ベーションの被覆面に露出した金属上のはんだ可能なパ
ッドの大きさによって制限される。BACKGROUND OF THE INVENTION Solder bump interconnects were developed to eliminate the high cost, unreliability, and low productivity of manual wire bonding. Solder bump interconnect technology for flip-chip integrated circuits has been used in some form for approximately 20 years. Whereas early, less complex integrated circuits typically have peripheral connections, flip-chip bumping technology allows for a significant increase in interconnect density as it progresses to full-area arrays. did. Controlled collapse chip connections use solder bumps deposited on wettable metal terminals on the die and matching footprints of the wettable terminals with solder on the substrate. An upside-down integrated circuit (flip chip) is aligned to the substrate and all bonds are formed by reflowing the solder at the same time. In the controlled collapse method, bumps of solder are deposited onto the terminals of an integrated circuit, and the solder bumps are restrained from flowing out of the terminals by the use of a thick glass dam, and the tip of the substrate metallization is Solder flow is restricted. Similarly, solder flow on an integrated circuit is limited by the size of the solderable pads on the exposed metal on the surface of the chemically vapor deposited glass passivation on the integrated circuit.
【0003】はんだ合金の選択は融点に基づき決定され
る。鉛の多いはんだは該合金の高い融点のため集積回路
をアルミナセラミックの基板に接合する場合に使用され
、組み立てられた回路のさらに他の処理を許容する。
エポキシまたはポリイミド回路板のような有機キャリア
への接合はより低い融点のはんだ合金を必要とする。共
融の錫/鉛はんだ(融点183℃)または鉛/インジュ
ウムはんだ(融点220℃)のようなはんだが使用され
ている。[0003] The selection of solder alloy is determined based on its melting point. Lead-rich solders are used in joining integrated circuits to alumina ceramic substrates due to the high melting point of the alloy, allowing further processing of the assembled circuits. Bonding to organic carriers such as epoxy or polyimide circuit boards requires lower melting point solder alloys. Solders such as eutectic tin/lead solder (melting point 183°C) or lead/indium solder (melting point 220°C) have been used.
【0004】端子の冶金の選択は選択されるはんだに依
存する。銀および金はよくない選択であるが、それはこ
れらが急速にはんだ内に溶解するからである。従って、
銅、錫、鉛、パラジウム、プラチナ、またはニッケルが
一般に回路板の端子のために使用されており、かつクロ
ム、チタン、またはニッケルの薄膜が一般に集積回路端
子として使用されている。The choice of terminal metallurgy depends on the solder selected. Silver and gold are poor choices because they dissolve quickly into the solder. Therefore,
Copper, tin, lead, palladium, platinum, or nickel are commonly used for circuit board terminals, and thin films of chromium, titanium, or nickel are commonly used as integrated circuit terminals.
【0005】はんだバンプはダイがまだウエーハの形で
ある間に集積回路端子上に配設される。ウエーハを切断
する前の最終的な操作は電気的な試験であり、この場合
柔らかいはんだが端子に接触するために使用される機械
的なプローブに対し接触パッドを提供する働きをなす。Solder bumps are placed on integrated circuit terminals while the die is still in wafer form. The final operation before cutting the wafer is an electrical test, where the soft solder serves to provide a contact pad for the mechanical probe used to contact the terminals.
【0006】集積回路を基板に接合するためには、フラ
ックス、水−ホワイトロジンまたは水溶性のフラックス
、が集積回路を定位置に保持するための一時的な接着剤
として基板上に付加される。アセンブリはリフロー温度
サイクルにさらされ、オーブンまたは炉の中でダイを基
板に接合する。はんだの表面張力がダイを基板の端子に
自己整列する助けとなる。リフローの後、フラックスの
残留物がダイの腐食を防止するために除去されなければ
ならない。塩素、フッ素または炭化水素の溶剤がロジン
を除去するために使用され、あるいは水溶性のフラック
スを除去するためには表面活性剤の水溶液が使用される
。ダイの基板への緊密な接近のため(典型的には0.0
01から0.004インチ、すなわち0.0254ミリ
メートルから0.102ミリメートル)、ダイの下から
フラックス残留物を除去することは高度なクリーニング
体制およびかなりの時間の消費を要求する困難な作業で
ある。全てのフラックス残留物の完全な除去を保証する
ことが産業上の多くの努力の課題であった。To bond an integrated circuit to a substrate, a flux, water-white rosin or water-soluble flux, is applied onto the substrate as a temporary adhesive to hold the integrated circuit in place. The assembly is subjected to a reflow temperature cycle to bond the die to the substrate in an oven or furnace. The surface tension of the solder helps the die self-align with the terminals on the board. After reflow, flux residue must be removed to prevent corrosion of the die. Chlorine, fluorine or hydrocarbon solvents are used to remove rosin, or aqueous solutions of surfactants are used to remove water-soluble fluxes. Due to the close proximity of the die to the substrate (typically 0.0
01 to 0.004 inches, or 0.0254 mm to 0.102 mm), removing flux residue from under the die is a difficult task requiring sophisticated cleaning regimes and considerable time consumption. Ensuring complete removal of all flux residues has been the subject of many industrial efforts.
【0007】クリーニングの後、アセンブリは電気的に
試験され、かつさらに環境的な保護を与えるためにパッ
ケージングが付加される。パッシベーション、封入、ま
たはカバーの付加が通常の方法である。封入の場合、液
体ポリマがダイの回りおよび下に付加される。歴史的に
は、ポリマの選択はシリコーン(silicones)
およびエポキシであり、エポキシがより多く好まれてい
た。エポキシのセラミック基板への付着はシリコーンに
比べて優れている。エポキシの膨脹係数はセラミック充
填剤を添加することによって低くすることができる。こ
れは基板と封入材との間に生ずる熱的ストレスを低減す
る。低い膨脹係数を備えたエポキシの接着剤の重要性は
フリップチップのアプリケーションに対しては強調しす
ぎることはない。硬化したエポキシは堅くかつシリコー
ンの柔軟性を持たない。従って、もしそれらの膨脹係数
が充填剤によって低くならなければ、初期のデバイスの
故障がダイのクラックの形成から生じ得る。無機充填剤
の使用もまた熱伝導率およびイオンの汚染物質のレベル
に影響を与える。After cleaning, the assembly is electrically tested and packaging is added to provide additional environmental protection. Passivation, encapsulation, or adding a cover are common methods. For encapsulation, liquid polymer is added around and under the die. Historically, the polymer of choice has been silicones.
and epoxy, with epoxy being more preferred. Epoxy adheres better to ceramic substrates than silicone. The expansion coefficient of epoxies can be lowered by adding ceramic fillers. This reduces the thermal stress created between the substrate and the encapsulant. The importance of epoxy adhesives with low coefficients of expansion cannot be overemphasized for flip chip applications. Cured epoxy is stiff and does not have the flexibility of silicone. Therefore, if their coefficient of expansion is not lowered by the filler, early device failure can result from the formation of cracks in the die. The use of inorganic fillers also affects thermal conductivity and ionic contaminant levels.
【0008】ダイおよび基板の間の非常に小さなギャッ
プは装置に対し最大の環境的保護を提供するためには完
全に満たされなければならない。デバイスを封入する過
去の努力は、米国特許第4,604,644号に述べら
れているように、ダイの中央部に欠如領域を残し、有機
レジンが該ダイの周辺に付加され、かつ前記空間に毛管
作用により引き入れられた。ダイの大きさが増大するに
応じて、毛管作用の制限された効力はより微妙なものと
なりかつダイのさらに大きな領域が保護されないままと
なった。The very small gap between the die and the substrate must be completely filled to provide maximum environmental protection for the device. Past efforts to encapsulate devices have left a void area in the center of the die, organic resin is added around the die, and the space is removed, as described in U.S. Pat. was drawn in by capillary action. As the size of the die increased, the limited effectiveness of capillary action became more subtle and larger areas of the die remained unprotected.
【0009】[0009]
【発明が解決しようとする課題】ダイの表面を封入する
他の方法は上記制限を、ダイの中央に位置する、基板の
穴を通して有機レジンを付加することにより克服しよう
と試みた。はんだ付けおよびクリーニング操作の後、封
入樹脂がダイの表面の完全なカバレージを保証するため
に、前記穴に付加されかつダイの周辺回りにも付加され
た。この方法は前記穴のために使用されない空間を提供
するために、回路のない基板の領域を確保する必要性を
生ずる。Other methods of encapsulating the surface of a die have attempted to overcome the above limitations by applying organic resin through a hole in the substrate located in the center of the die. After soldering and cleaning operations, encapsulant resin was applied to the holes and also around the periphery of the die to ensure complete coverage of the die surface. This method creates the need to reserve areas of the board free of circuitry to provide unused space for the holes.
【0010】明らかに、ダイ表面の完全なカバレージを
保証しかつ基板の利用できる領域の最大限の使用を許容
するフリップチップ集積回路を封入する改良された方法
が必要とされる。Clearly, there is a need for an improved method of encapsulating flip chip integrated circuits that ensures complete coverage of the die surface and allows maximum use of the available area of the substrate.
【0011】[0011]
【課題を解決するための手段および作用】簡単に言えば
、本発明によれば、フラックス剤(fluxing
agent)を含む接着材料が金属化パターンを有する
基板またははんだバンプされた電気的要素(コンポーネ
ント)に付加される。該コンポーネントは基板上に配置
されかつはんだリフローされる。リフロー段階の間、前
記フラックス剤ははんだの基板の金属化パターンへの付
着を促進しかつ接着材料は硬化されて基板およびコンポ
ーネントを機械的に相互接続しかつ封入する。[Means and effects for solving the problems] Briefly stated, according to the present invention, a fluxing agent (fluxing agent) is used.
An adhesive material containing a solder-bumped electrical component is applied to a substrate having a metallization pattern or a solder-bumped electrical component. The component is placed on the board and solder reflowed. During the reflow step, the fluxing agent promotes adhesion of the solder to the metallization pattern of the substrate and the adhesive material is cured to mechanically interconnect and encapsulate the substrate and components.
【0012】0012
【実施例】図1を参照すると、金属化パターン110を
有する基板100がスクリーン印刷、ステンシル、プリ
フォームの被着、または他のディスペンス手段によって
接着材料120で選択的に被覆される。接着材料120
はフラックス剤および硬化(curing)剤を含むよ
う処方され、それにより材料が室温で直ちに硬化されな
いようになっている。適切な接着材料の例はビィスフェ
ノール(bisphenol)Aおよびエピクロロヒド
リンから作られるエポキシ樹脂である。キュア剤または
硬化剤はアミン、無水物、または適切な反応物質でよい
。適切な硬化剤を有するポリエステル樹脂のような他の
2材料性樹脂システムを代わりに用いることができる。
フラックス剤の目的ははんだ操作に対するフラックス作
用を提供することである。アビエチン酸、アジピン酸、
アスコルビン酸、アクリル酸、クエン酸、2−フロイッ
ク酸(2−furoic acid)、リンゴ酸、お
よびポリアクリル酸がフラックス剤として有用であるこ
とが分かった。次のような一般式の他の有機酸もまた有
用であり、この場合、Rは電子吸引グループ(elec
tron withdrawing grorp)
である。特定の電子吸引グループはフッ素、塩素、臭素
、ヨウ素、硫黄、ニトリル、水酸基、ベンジルまたは何
らかの他の電子吸引グループである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a substrate 100 having a metallization pattern 110 is selectively coated with an adhesive material 120 by screen printing, stenciling, preform application, or other dispensing means. Adhesive material 120
The material is formulated to include a fluxing agent and a curing agent so that the material does not cure immediately at room temperature. An example of a suitable adhesive material is an epoxy resin made from bisphenol A and epichlorohydrin. The curing or curing agent may be an amine, anhydride, or a suitable reactant. Other two-material resin systems such as polyester resins with appropriate curing agents can be used instead. The purpose of the fluxing agent is to provide a fluxing action for the soldering operation. abietic acid, adipic acid,
Ascorbic acid, acrylic acid, citric acid, 2-furoic acid, malic acid, and polyacrylic acid have been found to be useful as fluxing agents. Other organic acids of the general formula are also useful, where R is an electron withdrawing group (elec
tron with drawing grorp)
It is. Particular electron-withdrawing groups are fluorine, chlorine, bromine, iodine, sulfur, nitrile, hydroxyl, benzyl or some other electron-withdrawing group.
【0013】接着材料におけるフラックス剤の量は、特
定のフラックス剤の活動、選択されたはんだ合金、およ
び基板の金属化システムに応じて、約0.1から約16
重量%の範囲とすることができる。The amount of fluxing agent in the adhesive material ranges from about 0.1 to about 16% depending on the specific fluxing agent activity, the selected solder alloy, and the substrate metallization system.
% by weight.
【0014】はんだバンプ140を含むデバイス130
ははんだバンプ140およびアクティブ面150が基板
100に面しかつ基板100の金属化パターン110と
整列するように配置される。図2を参照すると、バンプ
されたデバイス230が金属化パターン210との緊密
な接触へと移動される。接着剤220がデバイス230
を湿らせ、デバイス230のアクティブ面250の完全
な被覆を保証する。メニスカス260はアクティブ面2
50を環境汚染から保護するためにデバイス230の周
辺の回りに連続的な封入を提供する。接着剤220に含
まれているフラックス剤ははんだバンブ240および金
属化パターン210を覆う。Device 130 including solder bumps 140
Solder bumps 140 and active surface 150 are positioned facing substrate 100 and aligned with metallization pattern 110 of substrate 100 . Referring to FIG. 2, bumped device 230 is moved into intimate contact with metallization pattern 210. The adhesive 220 is attached to the device 230
to ensure complete coverage of the active surface 250 of the device 230. Meniscus 260 is active surface 2
A continuous encapsulation is provided around the periphery of the device 230 to protect the device 50 from environmental contamination. A fluxing agent contained in adhesive 220 covers solder bumps 240 and metallization pattern 210.
【0015】図面はデバイス130を基板に封入されか
つ接続される集積回路として描いているが、はんだバン
プを有する他のタイプの表面実装要素を用いた実施例も
本発明の範囲内であることを理解すべきである。Although the drawing depicts device 130 as an integrated circuit encapsulated and connected to a substrate, it is understood that embodiments using other types of surface mount elements with solder bumps are within the scope of the invention. You should understand.
【0016】アセンブリ270は伝統的な方法でリフロ
ーされ、フラックス剤が活性化されるようにし、はんだ
240および金属化面210の上の酸化物を減らし、か
つはんだの金属への合金化を許容する。リフロー処理の
間、接着剤(adhesive)220は固形に硬化さ
れる。使用された接着システムの化学に応じて、接着剤
220を完全に硬化するためにキュア後の第2の操作が
必要とされるかもしれない。リフロー/キュア段階の間
に、デバイスは接着剤により封入される。メニスカス2
40はアクティブ面250を環境汚染から保護するため
のデバイス230の周辺回りの連続的な封入を提供する
から、これ以上のクリーニングまたは封入操作は必要で
ない。Assembly 270 is reflowed in a traditional manner to allow the fluxing agent to be activated, reduce oxides on the solder 240 and metallized surfaces 210, and allow alloying of the solder to the metal. . During the reflow process, the adhesive 220 is cured to a solid state. Depending on the chemistry of the adhesive system used, a second post-cure operation may be required to fully cure adhesive 220. During the reflow/cure step, the device is encapsulated with adhesive. meniscus 2
40 provides a continuous encapsulation around the periphery of the device 230 to protect the active surface 250 from environmental contamination, so no further cleaning or encapsulation operations are required.
【0017】以下の実例は本発明を実施する態様を示す
ものであり、かつ不当にその範囲を限定することを意図
するものではない。The following examples are illustrative of the manner in which the invention may be practiced and are not intended to unduly limit its scope.
【0018】実例1
次の式によってフラックス剤および硬化剤を含む接着材
料が準備された。
成分
重量% Furane 89
303エポキシ、パートA 41
リンゴ酸
4.6 Furane 89303
エポキシ、パートB 54.4EXAMPLE 1 An adhesive material containing a fluxing agent and a hardening agent was prepared according to the following formula. component
Weight% Furane 89
303 Epoxy, Part A 41
malic acid
4.6 Furane 89303
Epoxy, Part B 54.4
【0019】Furane 89303エポキシ、パ
ートAはアメリカ合衆国、カリフォルニア州、ロサンゼ
ルスのFurane Products Comp
anyから入手可能なビィスフェノールA−エピクロロ
ヒドリン型のエポキシ樹脂である。それは半導体装置を
封入する用途のために処方されている。Furane
89303エポキシ、パートBはこれもまたFura
ne Products Companyから入手
可能な無水物硬化剤またはハードナーである。他のタイ
プの2材料(パート)エポキシもまた本発明の範囲内で
所望の結果を達成するために使用できる。等価な材料が
Hysol、Amicon、およびReichhold
Chemicalのような会社から入手可能である
。Furane 89303 epoxy, Part A, manufactured by Furane Products Comp, Los Angeles, California, USA.
It is a bisphenol A-epichlorohydrin type epoxy resin available from Any. It is formulated for use in encapsulating semiconductor devices. Furane
89303 epoxy, part B is also Fura
ne Products Company. Other types of two-part epoxies can also be used to achieve the desired results within the scope of this invention. Equivalent materials are Hysol, Amicon, and Reichhold
It is available from companies such as Chemical.
【0020】リンゴ酸およびエポキシのパートAがアル
ミニウムの平なべに入れられる。混合物は、溶液がクリ
アになるまで、かき混ぜながら約150℃に加熱された
。該溶液は室温まで冷却され、パートBが平なべに添加
され、かつ混合物は一様になるまでかき混ぜられた。
混合物の一部が銅被覆されたポリイミドフィルム上にへ
らでコーティングされ、かつ低温はんだ(63%錫、3
7%鉛)の球体が前記混合物の表面に置かれた。ポリイ
ミドフィルムがはんだ球のリフローを保証するために1
85℃を越える温度まで加熱された。約30秒の後、ポ
リイミドフィルムは熱源から除去されかつ室温まで冷却
された。はんだ球は30倍の顕微鏡の下で調べられリフ
ローの程度および球体の銅へのおよびまたお互いへのウ
エット状態が判定された。The malic acid and epoxy Part A are placed in an aluminum pan. The mixture was heated to approximately 150° C. with stirring until the solution became clear. The solution was cooled to room temperature, Part B was added to the pan, and the mixture was stirred until uniform. A portion of the mixture was spatula coated onto a copper-coated polyimide film and soldered with low temperature solder (63% tin, 3
A sphere of 7% lead) was placed on the surface of the mixture. 1. Polyimide film to ensure solder ball reflow
It was heated to a temperature exceeding 85°C. After approximately 30 seconds, the polyimide film was removed from the heat source and allowed to cool to room temperature. The solder balls were examined under a 30x microscope to determine the degree of reflow and wetting of the balls to the copper and to each other.
【0021】およそはんだ球の半分が大きな塊を形成す
るよう合体し、一方残りは合体せず明白な球体として留
まっていた。このことははんだが完全なリフローを保証
するために十分にウエットされていないことを示した。
ポリイミドフィルムの銅表面は接着剤が銅に接触してい
る所でつやがありかつ輝いており、銅酸化物の除去を示
していた。接着材料は堅くかつ銅に強固に接合している
ことが判明した。接着剤の差動走査熱量測定の試験によ
り接着剤が硬化したことが示された。Approximately half of the solder balls coalesced to form a large mass, while the remainder did not coalesce and remained as a distinct sphere. This indicated that the solder was not wet enough to ensure complete reflow. The copper surface of the polyimide film was glossy and shiny where the adhesive was in contact with the copper, indicating removal of copper oxide. The adhesive material was found to be stiff and bond strongly to the copper. Differential scanning calorimetry testing of the adhesive indicated that the adhesive had cured.
【0022】実例2
フラックス剤および硬化剤を含む他の接着材料が次の処
方に従って準備された。
成分
重量% Fura
ne 89303エポキシ、パートA
43.3 リンゴ酸
11.4 Fura
ne 89303エポキシ、パートB
45.3実例2が前記と同様にして製作されかつ
試験された。結果はおよそ70%のはんだ球が単一の塊
に合体したことを示した。Example 2 Another adhesive material containing a fluxing agent and a hardening agent was prepared according to the following recipe. component
Weight% Fura
ne 89303 epoxy, part A
43.3 Malic acid
11.4 Fura
ne 89303 epoxy, part B
45.3 Example 2 was constructed and tested in the same manner as above. The results showed that approximately 70% of the solder balls coalesced into a single mass.
【0023】実例3
フラックス剤および硬化剤を含む他の接着材料が次の処
方に従って準備された。
成分
重量% Fura
ne 89303エポキシ、パートA
41 リンゴ酸
16 Furane
89303エポキシ、パートB 4
3実例3が前記と同様にして製作されかつ試験された。
結果はすべてのはんだ球が単一の塊に合体し、はんだの
完全なかつ全部のウエッティングを示した。Example 3 Another adhesive material containing a fluxing agent and a hardening agent was prepared according to the following recipe. component
Weight% Fura
ne 89303 epoxy, part A
41 Malic acid
16 Furane
89303 Epoxy, Part B 4
3 Example 3 was constructed and tested in the same manner as described above. The results showed that all the solder balls coalesced into a single mass, indicating complete and total wetting of the solder.
【0024】実例4
フラックス剤および硬化剤を含む他の接着材料が次の処
方に従って準備された。
成分
重量% Shel
l Epon 825エポキシ樹脂
50 リンゴ酸
7 メチルヘキサハ
イドロフタリック無水物
42 イミダゾール
1Example 4 Another adhesive material containing a fluxing agent and a hardening agent was prepared according to the following recipe. component
Weight% Shel
l Epon 825 epoxy resin
50 Malic acid
7 Methylhexahydrophthalic anhydride
42 Imidazole
1
【0025】リンゴ酸(maric
acid)およびエポキシがアルミニウムの平なべに入
れられた。混合物は、溶液がクリアになるまで、かき混
ぜながら約150℃まで加熱された。該溶液は室温まで
冷却され、メチルヘキサハイドロフタリック無水物(m
ethylhexahydrophthalic a
nhydride)およびイミダゾールが平なべに加え
られ、かつ混合物は一様になるまでかき混ぜられた。[0025] Malic acid (maric acid)
acid) and epoxy were placed in an aluminum pan. The mixture was heated to approximately 150° C. with stirring until the solution became clear. The solution was cooled to room temperature and diluted with methylhexahydrophthalic anhydride (m
ethylhexahydrophthalic a
nhydride) and imidazole were added to the pan and the mixture was stirred until uniform.
【0026】該混合物の一部が上記と同様にして試験さ
れた。結果は75%のはんだ球が単一の塊に合体したこ
とを示し、はんだの不完全なウエッティングを示した。
これははんだが完全なリフローを保証するために十分に
ウエットされていないことを示した。ポリイミドフィル
ムの銅表面は接着剤が銅に接触している所ではつやがあ
りかつ輝いており、銅酸化物の除去を示していた。Sh
ell Epon 825エポキシ樹脂は175−
180のエポキシ等価量、および25℃において550
0−6500センチポイズの粘性を有する高純度ビスフ
ェノールA−エピクロロヒドリンのエポキシ樹脂である
。それはアメリカ合衆国、テキサス州、ヒューストンの
Shell Chemical Companyか
ら入手可能であり、かつイミダゾールはアメリカ合衆国
、ニュージャージ州、ニューワークの、Anhydri
de and Chemicals,Inc.から
入手可能である。A portion of the mixture was tested in the same manner as above. The results showed that 75% of the solder balls coalesced into a single mass, indicating incomplete wetting of the solder. This indicated that the solder was not wet enough to ensure complete reflow. The copper surface of the polyimide film was glossy and shiny where the adhesive was in contact with the copper, indicating removal of copper oxide. Sh
ell Epon 825 epoxy resin is 175-
Epoxy equivalent of 180 and 550 at 25°C
It is a high purity bisphenol A-epichlorohydrin epoxy resin with a viscosity of 0-6500 centipoise. It is available from Shell Chemical Company, Houston, Texas, USA, and the imidazole is available from Anhydri, Newark, New Jersey, USA.
de and Chemicals, Inc. Available from.
【0027】実例5
フラックス剤および硬化剤を含む他の接着材料が次の処
方に従って準備された。
成分
重量%
Furane 89303エポキシ、パートA
43.5 リンゴ酸
12.5
Furane 89303エポキシ、パートB
44実例5が上記と同様にして製作され
かつ試験された。結果はすべてのはんだ球が単一の塊に
合体したことを示し、はんだの完全なかつ全部のウエッ
ティングを示した。実例3に比較してより少ない量のフ
ラックス剤の使用が好ましいし実施例となることが決定
された。Example 5 Another adhesive material containing a fluxing agent and a hardening agent was prepared according to the following recipe. component
weight%
Furane 89303 epoxy, part A
43.5 Malic acid
12.5
Furane 89303 epoxy, part B
44 Example 5 was constructed and tested in the same manner as above. The results showed that all the solder balls coalesced into a single mass, indicating complete and total wetting of the solder. It was determined that the use of a lower amount of fluxing agent as compared to Example 3 was preferred and would be an example.
【0028】実例5の処方がフリップチップ集積回路の
はんだバンプされた出力端子を受け入れるために金属化
された5つの試験用基板をコーティングするために使用
された。バンプされた集積回路が実施例に述べられたよ
うにリフローされ、かつ電気的に試験された。全ての5
つの回路は電気的試験に合格した。はんだ付けされたア
センブリは次に交互に熱い液体バスおよび冷たい液体バ
スに浸すことにより熱サイクルにさらされた。加熱され
たバスの温度は125℃でありかつ冷たいバスの温度は
−55℃であり、はんだ付けされたアセンブリは各々の
バスに1分間留められその後直ちに他のバスに移された
。アセンブリは1,5,10,25,50,100,1
25,175,および200の熱サイクルの後同じ電気
的試験体制に提出された。すべての5つのアセンブリは
175の熱サイクルを経た電気的試験に合格し、1つの
アセンブリが200サイクルで試験に不合格となった。The formulation of Example 5 was used to coat five test substrates that were metallized to accept solder bumped output terminals of flip chip integrated circuits. The bumped integrated circuits were reflowed and electrically tested as described in the Examples. all 5
One circuit passed the electrical test. The soldered assembly was then subjected to thermal cycling by immersing it in alternating hot and cold liquid baths. The temperature of the heated bath was 125°C and the temperature of the cold bath was -55°C, and the soldered assemblies remained in each bath for 1 minute and were then immediately transferred to the other bath. Assembly is 1, 5, 10, 25, 50, 100, 1
They were submitted to the same electrical test regime after 25, 175, and 200 thermal cycles. All five assemblies passed the electrical test after 175 thermal cycles, with one assembly failing the test after 200 cycles.
【0029】実例5の処方はまたフリップチップ集積回
路のはんだバンプされた出力端子を受け入れるために金
属化された3つの試験用基板をコーティングするために
使用された。バンプされた集積回路は実施例に述べたよ
うにリフローされ、かつ機械的試験に付された。力測定
用ツールのかなとこ(anvil)が集積回路の側部に
対して配置されかつ集積回路を基板から取り外すのに必
要な力が記録された。その力は3.8から4.7ニュー
トンにおよび、平均の力は3.9ニュートンであった。The formulation of Example 5 was also used to coat three test substrates that were metallized to accept solder bumped output terminals of flip chip integrated circuits. The bumped integrated circuits were reflowed and mechanically tested as described in the Examples. The anvil of a force measuring tool was placed against the side of the integrated circuit and the force required to remove the integrated circuit from the substrate was recorded. The forces ranged from 3.8 to 4.7 newtons, with an average force of 3.9 newtons.
【0030】[0030]
【発明の効果】以上のように、本発明によれば、フラッ
クス特性を有する接着剤が表面実装コンポーネント、特
にフリップチップ集積回路、をはんだリフローしかつ封
入するために使用することができ、集積回路のアクティ
ブ面の完全な環境的保護を提供する。As described above, according to the present invention, an adhesive having flux properties can be used to solder reflow and encapsulate surface-mounted components, particularly flip-chip integrated circuits, Provides complete environmental protection for active surfaces.
【図1】本発明に従って基板に取り付ける前のデバイス
の断面的正面図である。1 is a cross-sectional front view of a device prior to attachment to a substrate according to the invention; FIG.
【図2】本発明に従って基板にリフローした後のデバイ
スを示す断面的正面図である。FIG. 2 is a cross-sectional front view showing a device after reflow to a substrate according to the present invention.
100,200 基板 110,210 金属化パターン 120,220 接着材料 130,230 デバイス 140,240 はんだバンプ 150,250 アクティブ面 260 メニスカス 270 アセンブリ 100,200 board 110,210 metallization pattern 120,220 Adhesive material 130,230 device 140,240 Solder bump 150,250 active surface 260 meniscus 270 Assembly
Claims (10)
ネント装着基板の間の電気的および機械的相互接続を行
う方法であって、金属化パターンを有する基板を提供す
る段階、はんだバンプをそこに有する電気的コンポーネ
ントを提供する段階、フラックス剤を含む接着材料を前
記基板または前記コンポーネントに付加する段階、前記
基板上に前記コンポーネントを位置付ける段階、そして
前記はんだバンプをリフローする段階であって、前記フ
ラックス剤がはんだの基板金属化パターンへの接着を促
進しかつ前記接着材料が硬化されて機械的に前記基板と
前記コンポーネントを相互接続するもの、を具備するこ
とを特徴とする電気的コンポーネントおよびコンポーネ
ント装着基板の間の電気的および機械的相互接続を行う
方法。1. A method of making electrical and mechanical interconnections between an electrical component and a component-mounted substrate, comprising: providing a substrate with a metallization pattern; applying an adhesive material including a fluxing agent to the substrate or the component; positioning the component on the substrate; and reflowing the solder bump, wherein the fluxing agent is attached to the substrate of the solder. an electrical connection between an electrical component and a component mounting substrate, characterized in that the adhesive material promotes adhesion to a metallization pattern and, when the adhesive material is cured, mechanically interconnects the substrate and the component. methods of making physical and mechanical interconnections.
記接着材料を第1の温度で加熱してはんだリフローを行
う段階であって、前記フラックス剤が前記はんだバンプ
のリフローを促進するもの、そして前記接着材料を第2
の温度で加熱して前記接着材料の硬化を行う段階、を具
備することを特徴とする請求項1に記載の方法。2. The step of reflowing the solder is a step of heating the adhesive material at a first temperature to perform solder reflow, the fluxing agent promoting reflow of the solder bump, and the step of reflowing the solder bump. Add the adhesive material to the second
2. The method of claim 1, further comprising the step of curing the adhesive material by heating at a temperature of .
互接続するためのはんだリフローに使用するためのフラ
ックス剤を有する接着材料であって、熱硬化樹脂、フラ
ックス剤、および硬化剤を具備することを特徴とするフ
ラックス剤を有する接着材料。3. An adhesive material having a fluxing agent for use in solder reflow for interconnecting electrical components and substrates, comprising a thermosetting resin, a fluxing agent, and a hardening agent. Adhesive material with a fluxing agent.
る化合物を具備し、この場合Rは電子吸引グループであ
ることを特徴とする請求項3に記載の接着材料。4. The adhesive material of claim 3, wherein the fluxing agent comprises a compound having the following formula: where R is an electron-withdrawing group.
、硫黄、水酸基、ニトリル、およびベンジルからなるグ
ループから選択されることを特徴とする請求項3に記載
のフラックス剤。5. The fluxing agent of claim 3, wherein R is selected from the group consisting of fluorine, chlorine, bromine, iodine, sulfur, hydroxyl, nitrile, and benzyl.
とを特徴とする請求項3に記載の接着材料。6. The adhesive material according to claim 3, wherein the fluxing agent is malic acid.
割合は前記接着材料の約0.1から約16重量%の範囲
であることを特徴とする請求項3に記載の接着材料。7. The adhesive material of claim 3, wherein the proportion of fluxing agent in the adhesive material ranges from about 0.1 to about 16% by weight of the adhesive material.
ンポーネントであって、各終端部ははんだバンプを含む
もの、前記電気的コンポーネントの終端部に対応する複
数の電気的終端部を有するコンポーネント装着基板、前
記電気的コンポーネントを前記基板に機械的に接続する
ための接着材料であって、エポキシ樹脂、硬化剤、そし
てフラックス剤、を具備するもの、を具備し、前記接着
材料は前記電気的コンポーネントおよび基板の間に配置
されかつこれらを接合し、前記はんだバンプはリフロー
されかつ前記電気的コンポーネントを基板に電気的に接
続することを特徴とする、電気的コンポーネントアセン
ブリ。8. An electrical component having a plurality of electrical terminations, each termination including a solder bump, a component mounting having a plurality of electrical terminations corresponding to the terminations of the electrical component. a substrate, an adhesive material for mechanically connecting the electrical component to the substrate, the adhesive material comprising an epoxy resin, a hardening agent, and a fluxing agent; and a substrate, the solder bumps being reflowed and electrically connecting the electrical component to the substrate.
る化合物を具備し、この場合Rはフッ素、塩素、臭素、
ヨウ素、硫黄、水酸基、ニトリル、およびベンジルから
なるグループから選択された電子吸引グループであるこ
とを特徴とする請求項8に記載の電気的コンポーネント
アセンブリ。9. The fluxing agent comprises a compound having the following formula: where R is fluorine, chlorine, bromine,
9. The electrical component assembly of claim 8, wherein the electron withdrawing group is selected from the group consisting of iodine, sulfur, hydroxyl, nitrile, and benzyl.
特徴とする請求項9に記載の電気的コンポーネントアセ
ンブリ。10. The electrical component assembly of claim 9, wherein the compound is malic acid.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US588,888 | 1990-09-27 | ||
| US07/588,888 US5128746A (en) | 1990-09-27 | 1990-09-27 | Adhesive and encapsulant material with fluxing properties |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04280443A true JPH04280443A (en) | 1992-10-06 |
| JP2589239B2 JP2589239B2 (en) | 1997-03-12 |
Family
ID=24355725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3272090A Expired - Fee Related JP2589239B2 (en) | 1990-09-27 | 1991-09-24 | Thermosetting adhesive and electrical component assembly using the same |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5128746A (en) |
| JP (1) | JP2589239B2 (en) |
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| US4448847A (en) * | 1982-05-28 | 1984-05-15 | Shell Oil Company | Process for improving steel-epoxy adhesion |
| US4604644A (en) * | 1985-01-28 | 1986-08-05 | International Business Machines Corporation | Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making |
| US4980086A (en) * | 1985-10-16 | 1990-12-25 | Toagosei Chemical Industry, Co., Ltd. | Curable composition |
| US4855001A (en) * | 1987-02-10 | 1989-08-08 | Lord Corporation | Structural adhesive formulations and bonding method employing same |
-
1990
- 1990-09-27 US US07/588,888 patent/US5128746A/en not_active Expired - Lifetime
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2589239B2 (en) | 1997-03-12 |
| US5128746A (en) | 1992-07-07 |
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