JPH0428184B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a signal processing device that processes frequency characteristics of an input signal such as a video signal.

Conventional configurations and their problems In video tape recorders (hereinafter abbreviated as VTR) that record and playback video signals,
In a frequency modulation/demodulation system, if the noise on the FM transmission line is white noise, the noise added to the demodulated signal exhibits so-called triangular noise characteristics, in which the noise level increases as the frequency increases. In order to reduce this, before frequency modulation, the level of the middle and high frequencies of the input signal is increased (so-called emphasis is applied to increase the frequency deviation width).
After frequency demodulation, signal processing is performed to lower the levels of the middle and high frequencies (so-called de-emphasis). However, the band of the FM transmission line is limited by the electromagnetic conversion system, etc., so there is a limit to the increase in frequency deviation width due to the amount of emphasis, which limits the S/N ratio of the reproduced signal. There was a problem. In addition, this problem
This is a problem that occurs not only in VTRs but also in all systems that frequency-modulate and transmit video signals, such as satellite broadcasting.

FIG. 1 is an image diagram of a conventional emphasis circuit used in VHS system VTRs and the like. In Fig. 1, the video signal applied to input terminal 1 is
The signal is outputted to the output terminal 5 via the emphasis circuit 50. The AF system circuit 50 includes a capacitor (capacitance value C ₁ ) 51, a resistor (resistance value Rb) 52, and a resistor (resistance value Ra) 53. Their values are
For example, C ₁ ×Rb=1.3μsec, (Ra+Rb)/Ra=5.

When a video signal as shown in FIG. 2a is input to such a circuit, a signal as shown in FIG. 2b is obtained at the output terminal.

In the case of a VTR, the signal shown in Figure 2b is frequency-modulated and recorded on a magnetic tape (not shown), but because the frequency band of the electromagnetic conversion system, which is the FM transmission path, is limited, The signal is clipped at the point indicated by the broken line S in FIG. 2b, and the signal is frequency-modulated as shown in FIG. 2c. Alternatively, by changing the constants of each part of the emphasis circuit 50 and setting the emphasis amount (=Rb+Ra/Ra) to 1/2, for example, a signal as shown in FIG. 2d can be obtained.
Frequency modulation. In the case of Fig. 2c, there is a problem that waveform distortion occurs, and in the case of Fig. 2d,
There is a problem in that the effect of the emphasis is reduced to 1/2, and the S/N ratio of the reproduced signal decreases by that amount.

Purpose of the Invention The present invention solves the above-mentioned conventional problems, and provides a signal processing device that can use a larger amount of emphasis than the conventional one with the same frequency shift width as the conventional one, using the same FM transmission path. The purpose is to provide the following. Alternatively, it is an object of the present invention to provide a signal processing device in which the peak value of a waveform is significantly lower than that of the conventional art even when the amount of emphasis is the same as that of the conventional art. A further object of the present invention is to provide a signal processing device having arbitrary transfer characteristics including preshoot and overshoot. Another object of the present invention is to provide a signal processing device that can compensate for the phase characteristics of a transmission circuit and zero out the phase change of a processed signal in real time.

Configuration of the Invention The signal processing device of the present invention includes a first switch;
nH (however,
n: any positive integer; H: horizontal scanning period); a second switch that operates with a time delay; a second transmission circuit having the same transfer function G as the first transmission circuit; and a second memory. a third switch operating 2nH later than the first switch, a third transmission circuit having the same transfer function G as the first transmission circuit, a third memory circuit, The first, second, and third memory circuits sequentially input signals over a period (nH+α+β) from time α before the nH period to time β after the nH period, respectively. The input signal is configured to be output in reverse time series over the (nH+α+β) period, and the first switch is connected to the input terminal side for the (nH+α+β) period,
The input signal is stored in the first memory circuit via the first transmission circuit in the first (nH+α+β) period, and is read out from the first memory circuit in reverse chronological order in the next (nH+α+β) period. Served, first
After passing through the second transmission circuit, the signal is again input to the fourth switch via the first transmission circuit, and in the same way, the signal that has passed through the second transmission circuit is input to the second transmission circuit for a period of (nH+α+β). is stored in the memory circuit, and in the next (nH+α+β) period, the second
are read out in reverse chronological order from the memory circuit of
After passing through the second switch, it is again input to the fourth switch via the second transmission circuit, and the third
The signal that has passed through the transmission circuit is stored in the third memory circuit, and in the next (nH+α+β) period, it is read out from the third memory circuit in reverse time series,
After passing through the third switch, the signals are input to the fourth switch via the third transmission circuit again, and the output signals of the first, second, and third transmission circuits are input to the fourth switch. It is configured such that the signals are switched every nH period and output as one series of signals.

DESCRIPTION OF EMBODIMENTS The present invention will be described below based on illustrated embodiments.

FIG. 3 shows a block diagram of the signal processing device 34 of the present invention. In addition, since an emphasis circuit will be described here as an example of the signal processing device 34, the signal processing device 34 will be hereinafter referred to as an emphasis circuit 34. Now, consider the case where the signal shown in FIG. 4a is input to the input terminal 1.
Now, if n = 1, (nH + α + β) period closes,
The first switch 3 opens for the next (2nH-α-β) period
The signal that has passed through the first transmission circuit 6 becomes as shown in FIG. 4b. From the first switch 3
The signal that has passed through the second transmission circuit 7 via the second switch 4, which operates with a delay of nH time, is transferred to the fourth switch 4.
Similarly, the third transmission circuit 8 outputs a signal as shown in FIG. 4d, which is delayed by 2nH from that in FIG. 4b. The signal in Figure 4b is (nH+α
+β) period, and is stored in the first memory circuit 9 over the next (nH+α+β) period,
It is output in the reverse chronological order from when it was memorized, as shown in Figure 4 e.
The waveform will be like this. Similarly, the second memory circuit 10 and the third memory circuit 11 output signals as shown in FIG. 4f and g, respectively. Fourth
When the signals shown in Figures e, f, and g pass through the first, second, and third transmission circuits 6, 7, and 8, respectively, they pass through the fourth transmission circuit.
The waveforms are as shown in Figures h, i, and j. The fourth switch 12 switches every nH time to 1.
When output as a series signal, the departure terminal 2 will have
As shown in FIG. 4k, one series of signals having a preshoot and an overshoot appears.

Here, the feature of the present invention is that the period of the input signal to be processed is (nH+α) from time α before nH time to time β after time nH.
+β) period and the input signal is the first, second
and passes through the third transmission circuits 6, 7, and 8 twice each.

When the input signal passes through the input signal for the first time, it becomes a positive time series, and when it passes through the input signal for the second time, it becomes a negative time series. Therefore,
The signal flow is shown in FIG. 5. 1st
The input signal to the transmission circuit 61 is x(n), the output signal of the transmission circuit 61 is f(n), the output signal of the first time series inversion circuit 62 is a(n), and the output signal of the transmission circuit 63 is b(n), and the unit impulse responses of the transmission circuits 61 and 63 are each h(n). The z transformation of each signal is expressed as X(z), F(z), A(z), B(z
)
Then, F(z)=H(z)X(z) A(z)=F(z ^-1 )=H(z ^-1 )X(z ^-1 ) B(z)=H(z)A (z) = H( ^z ) ^H (z ^{-1 )} )=B(z)/(z ^-1 )=H(z ^-1 )H(z). However, the output signal of the system shown in FIG. 5 has a time series opposite to that of the input signal. If it is desired to obtain a signal in the same time series as the input signal, a time series reverse rotation may be connected to the output end of the system shown in FIG. When the equivalent impulse response of the system shown in FIG. 5 is expressed by Fourier transform, Heq(e ^j 〓)=|H(e ^j 〓)| ² , and the phase change is zero. This zero-phase characteristic is desirable in video signal processing, and can be achieved with the circuit configuration shown in FIG. 3. In particular, in the configuration of FIG. 5, the transmission circuits 61 and 6
However, in Figure 3, the signal passes through the same circuit twice, so the phase characteristics of the transmission circuit cancel each other out, making it difficult to achieve a complete zero phase. Zero phase can be achieved. Also, the fifth
The gain of the system shown in the figure is the square of the one-stage transmission circuit. Therefore, if the required gain is G, the gain of one stage of the transmission circuit in the system shown in FIG. 5 must be √. first, second, and third transmission circuits 6,
7 and 8 are emphasis circuits 30 as shown in FIG. The emphasis circuit 30 includes a capacitor (capacitance value C ₂ ) 31, a resistor (resistance value Rc) 32,
It is composed of a resistor (resistance value Rd) 33. For these values, since the same signal passes through the first, second, and third transmission circuits 6, 7, and 8 twice, the amount of emphasis is squared as described above. Therefore, Rc+Rd/Rd=5 is set for the conventional example shown in FIG.

As a result of the emphasis, a signal as shown in FIG. 4a is input to the first switch 3, and after signal processing, when it reaches the fourth switch 12, it becomes a signal as shown in FIG. 4h. The signal in Fig. 4h has a waveform with preshoot and overshoot, so even though the amount of emphasis is the same as that of the conventional example shown in Fig. 1, its peak value is a waveform lower than the broken line S. is obtained. However, Fig. 4h
In the waveform of , unnecessary waveform changes appear in the pre-β period and the post-α period of H time. This is to separate the continuous signal and perform emphasis processing as a signal of the (nH + α + β) period. By switching the switch 12, a signal as shown in FIG. 4k can be obtained.

Note that in the above description, n=1, but n2 may also be used. In addition, although the transmission circuit was made into three systems,
Similar effects can be obtained by using four or more systems.
In addition, the first, second, and third memory circuits 9, 10,
11 is analog memory (for example, charge
Each memory circuit has an AD (analog-to-digital) converter at the input end and a DA (digital-to-analog) converter at the output end, and can be used as a memory. may be a digital memory configured with a flip-flop circuit or the like. In addition, the first, second, and third switches 3, 4,
It has an AD converter before the input terminal of No. 5, and
The second and third memory circuits 9, 10, and 11 are digital memories composed of flip-flop circuits, etc., and the first, second, and third transmission circuits 6, 7, and 8
The same operation can be performed even if the switch is configured with a digital filter and a DA converter is provided after the fourth switch 12. Furthermore, A before input terminal 1
It has a converter, the first, second and third memory circuits 9, 10 and 11 are digital memories constituted by flip-flop circuits, etc., and the first, second and third transmission circuits 6, 7 and 8 are The same operation can be achieved even if the filter is configured with a non-recursive digital filter or a recursive digital filter and is later provided with a DA converter via the output terminal 5.

Furthermore, in the above description, the video signal was used as the input signal, so the first, second, and third memory circuits 9, 10, and 11 or the first, second, third, and fourth switches 3, The operations of 4, 5, and 12 are
In all cases, the unit is a period based on H, such as H and H+α+β, but depending on the input signal, the unit may be set to any time. Further, in the above description, the emphasis circuit was explained, but it may also be used in a circuit for the purpose of providing preshoot or overshoot, as shown in FIG. 4k. Also, in the above explanation, an output signal in reverse time series is obtained with respect to the input signal, but it is also possible to further reverse the time series of the output signal from the above circuit and convert it into a simultaneous series and output with the input signal. do not have.

Effects of the Invention As described above, the signal processing device of the present invention has 1
By passing the signal through the transmission circuit in the positive time series and then outputting it through the same transmission circuit in the reverse time series, it has the effect of making the phase characteristic of the transmission circuit zero phase, and the video signal is particularly useful.
In addition, when processing continuous signals by dividing them, (nH + α + β) from time α before nH period to time β after
Since period processing is performed, the α period and β period near discontinuous portions of the signal can be avoided and output, and unnecessary waveform changes will not be imparted to the output signal. In addition, by performing the above processing in three series, the task of dividing a continuous signal into sections, processing them, and outputting them again as a continuous signal can be done.
Can be executed in real time.

Furthermore, as described above, when the signal processing device of the present invention is used as a frequency modulation type emphasis circuit, by giving the waveform a preshoot and an overshoot, it can have the same amount of emphasis as the conventional one. It is possible to realize an emphasis circuit in which the peak value of the waveform is significantly lower than that of the conventional technique, and the frequency deviation width can be significantly reduced compared to the conventional technique without reducing the amount of emphasis. Alternatively, if the same frequency shift width as before is used, more emphasis than before can be added, and the reproduced signal can be improved.

[Brief explanation of drawings]

Fig. 1 is a wiring diagram showing an example of a conventional emphasis circuit, Fig. 2 is a signal waveform diagram of Fig. 1, Fig. 3 is a main part block diagram showing an example of the signal processing device of the present invention, and Fig. 4 is Fig. 3 is a signal waveform diagram of each part, Fig. 5 is a block diagram explaining the concept used to realize zero-phase characteristics in the present invention, and Fig. 6 is a wiring diagram showing an example of the emphasis circuit used in the present invention. It is a diagram. 3...First switch, 4...Second switch, 5...Third switch, 6...First transmission circuit, 7...Second transmission circuit, 8...Third transmission circuit , 9...first memory circuit, 10...second memory circuit, 11...third memory circuit, 12...
Fourth switch, 34...signal processing device.

Claims (1)

[Claims] 1 a first switch and a first switch whose transfer function is G
transmission circuit, a first memory circuit, and the first switch nH (where n: any positive integer,
H: horizontal scanning period) a second switch that operates with a time delay, a second transmission circuit having the same transfer function G as the first transmission circuit, a second memory circuit, and the first switch. a third switch that operates 2nH later than the first transmission circuit; a third transmission circuit having the same transfer function G as the first transmission circuit;
a memory circuit, and a fourth switch, the first, second, and third memory circuits each having a
From time α before nH period to time β after (nH+
The first switch is configured to sequentially input signals over a period of (α+β) and output the inputted signals in reverse time series over the next (nH+α+β) period. nH+α+β) period input terminal side, and the input signal is stored in the first memory circuit via the first transmission circuit in the first (nH+α+β) period, and is stored in the first memory circuit during the next (nH+α+β) period.
+α+β) period, the data is read out from the first memory circuit in reverse chronological order, passed through the first switch, and then inputted again to the fourth switch via the first transmission circuit, and the same and (nH+α+
The signal that has passed through the second transmission circuit is stored in the second memory circuit over the period β), and is read out from the second memory circuit in reverse time series in the next (nH+α+β) period. After passing through the second switch, the signal is again input to the fourth switch via the second transmission circuit, and (nH+
The signal that has passed through the third transmission circuit over a period of α+β) is stored in the third memory circuit, and is read out in reverse time series from the third memory circuit in the next (nH+α+β) period, After passing through the third switch, the signal is inputted to the fourth switch via the third transmission circuit again, and the first, second,
A signal processing device characterized in that the output signal of the third transmission circuit is configured to be switched by the fourth switch every nH period and output as one series of signals.