JPH04282930A - Asynchronous trigger transmission circuit - Google Patents

Abstract

PURPOSE:To attain high speed data transfer due to optimum timing synchronization with respect to the asynchronous trigger transfer circuit in an information processing unit. CONSTITUTION:The circuit consists of a synchronization circuit 13 synchronizing an inputted taus trigger with taui synchronization, a differentiating circuit 14 differentiating an output of the synchronization circuit 13, and a changeover circuit 15 switching the timing when the taui trigger is generated from the output of the differentiating circuit 14 with the period ratio of taus and taui. Since the taus trigger is synchronized with the taui synchronization, the synchronization output is differentiated and the timing to generate the taui trigger from the differentiating output is switched by the period ratio of the taus and taui, the taui trigger is validated at the leading of the synchronization circuit and the differentiating circuit. Thus, since the timing to send the taui trigger is optimized, high speed data transfer is implemented.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous trigger transmission circuit in an information processing apparatus that performs asynchronous data transfer processing. In information processing equipment, asynchronous control is often performed between channels and external devices, system common buses and asynchronous processors, etc., but as the speed of processors and channels has increased due to recent advances in semiconductor technology, asynchronous signal transmission There is a demand for faster speeds.

0002

[Prior Art] As a conventional asynchronous trigger transmission circuit,
For example, there is one shown in FIG. 1 to 3 are D flip-flops, and these D flip-flops 1 to 3 are D flip-flops.
3 outputs signal a, signal b, and signal c, respectively.

4 is an AND circuit, and the AND circuit 4 receives the signal c of the D flip-flop 3 and the D flip-flop 2.
The inverted signal d of is input. Since τs and τi are asynchronous, they must be synchronized, so the τs trigger is synchronized by D flip-flop 1 and D flip-flop 2, and D
A flip-flop 3 takes a differential, and an AND circuit 4 generates a τi trigger.

Next, a time chart of the asynchronous trigger transmission circuit is shown in FIG. In FIG. 14, A is an address on the interface, and since it takes time to determine the address, B is the address once received in the buffer. C is an address where B is further buffered. The figure shows an arrangement in which an address A of the τs synchronization interface is monitored, a τs trigger is generated by the address A, the trigger is synchronized with τi, and the τi synchronization unit controls the trigger.

[0005] In the figure, SPT10, SPT20A, SPT
30A and SPT40A respectively mean the stages of the τs synchronization interface, and τs at the timing of SPT10.
Address A is output on the synchronous interface. SP
Address A is output on the interface at timing T10, and is set as address B in the buffer at the trailing edge of SPT10.

Furthermore, the address B set in the buffer
is set as address C in the buffer at the trailing edge of SPT20A. The address B set in the buffer is monitored at the timing of the SPT 20A, and when a trigger for the τi synchronization control unit occurs, the τs trigger is turned on. The τs trigger is synchronized and passed to the τi synchronization control unit.

As shown in the figure, the τi trigger becomes valid at the falling edge of the signals b and c.

[0008]

However, in such a conventional asynchronous trigger transmission circuit, as shown in FIG. 14, when τi and τs are approximately equal and when τi<
If <τs, the falling differential of the trigger must be used when synchronizing (c is not yet determined in the rising differential of the trigger), so the timing of synchronization is fixed at the worst case, and high-speed There was a problem in that it was not possible to perform data transfer.

The present invention has been made in view of these conventional problems, and an object of the present invention is to provide an asynchronous trigger transmission circuit that can perform high-speed data transfer through optimal timing synchronization. It is said that

0010

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, 13 is a synchronization circuit that synchronizes the input τs trigger with τi synchronization, 14 is a differentiation circuit that takes the differential of the output of the synchronization circuit 13, and 15 is the differentiation circuit 1
This is a switching circuit that switches the timing of generating the τi trigger from the output of 4 according to the period ratio of τs and τi.

[0011]

[Operation] In the present invention, the τs trigger is synchronized with the τi synchronization, the synchronous output is differentiated, and the timing at which the τi trigger is generated from the differential output is switched depending on the period ratio of τs and τi. The τi trigger becomes valid at the rising edge of the differentiating circuit.

[0012] As described above, since the timing of transmitting the τi trigger is optimized, high-speed data transfer can be performed.

[0013]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings. 2 to 5 are diagrams showing an embodiment of the present invention (in the case of a single trigger). In FIG. 2, 11 is a D flip-flop that outputs signal e, and 12 is a D flip-flop that outputs signal b.
These D flip-flops 11 and 12 constitute a synchronization circuit 13 that synchronizes the τs trigger with the τi synchronization.

Reference numeral 14 denotes a D flip-flop to which signal b is input and signals g and i are output. 15 is a switching circuit that switches the timing of generating the τi trigger from the output of the D flip-flop (differentiator circuit) 14 according to the period ratio of τs and τi;
The switching circuit 15 is composed of AND circuits 16, 17, 18, a D flip-flop 19, and an OR circuit 20.

[0015] The period ratio of τs and τi is τi<τs/2,
There are three cases: τs/2<τi<τs and τi≧τs. If τi<τs/2, τi is
A trigger is generated, and if τs/2<τi<τs, a τi trigger is generated via the AND circuit 18, and τi<≧τ
In the case of s, a τi trigger is generated via the AND circuit 17. In the figure, (1) is a signal “1” when τi<τs/2
, (2) indicates a means for outputting a signal "1" when τs/2<τi<τs, and (3) indicates a means for outputting a signal "1" when τi≧τs, and is composed of switches, registers, etc. Ru.

Next, a time chart in the case of τi<τs/2 is shown in FIG. In FIG. 3, since τs and τi are asynchronous, they must be synchronized, and the D flip-flop 11
, 12 and differentiated by the D flip-flop 14, and the τi trigger is enabled at the falling edge of the D flip-flops 12 and 14. In this way, through the AND circuit 16, τ
An i-trigger is generated and transmitted to address C, and data transfer occurs.

When the signal b is off and the signal g is on, the τi trigger becomes valid at the falling edge. This is the same as before. Next, a time chart in the case of τs/2<τi<τs is shown in FIG. In FIG. 4, since τs and τi are asynchronous, they must be synchronized, and the D flip-flop 1
1 and 12, differentiated by the D flip-flop 14, and at the rise of the D flip-flops 12 and 14, τ
Enable i-Trigger.

Once received by the D flip-flop 19 via the AND circuit 17, a τi trigger is generated via the AND circuit 18, and transmitted to the address C, where data transfer is performed. Here, the reason why the signal is received by the D flip-flop 19 is that the timing for transmitting it to the address C is difficult.

In this case, when the signal h is on and the signal g is off, the τi trigger becomes valid at the rising edge. Next, a time chart in the case of τi≧τs is shown in FIG. In FIG. 5, τi and τs are asynchronous, and are synchronized by D flip-flops 11 and 12, differentiated by D flip-flop 16, and the τi trigger is enabled at the rising edge of D flip-flops 12 and 14.

A τi trigger is generated via the AND circuit 17 and transmitted to address C, and data transfer is performed. In this case as well, when the signal b is on and the signal g is off, the τi trigger becomes valid at the rising edge. Next, Figures 6 to 12
FIG. 7 is a diagram showing another embodiment (in the case of continuous triggers) of the present invention.

In FIG. 6, SCLK is a clock synchronized with the τs trigger, ICLK is a clock synchronized with the τi trigger, and ST1 to ST4 are AND circuits 21 to 24.
τs trigger set signal output by T flip-flop 25, ITRGAT is a trigger signal output by T flip-flop 25, ITRGAT
is the trigger signal output by the T flip-flop 26, IT
RGB is a synchronization signal output from the D flip-flop 11, ITRGC is a synchronization signal output from the D flip-flop 12, ITRGD is a differential signal output from the D flip-flop 14, and ITRGE is an exclusive OR circuit 2.
7 is a signal output, l is a signal output from the T flip-flop 28, m is a signal output from the T flip-flop 29, ID1 to ID4 are buffer select signals, and k is an output signal from the D flip-flop 19.

Further, 30 to 33 are a plurality of holding circuits (buffers) for holding the τs trigger, 34 to 45, 46 to 48
is an AND circuit, and 49 to 54, 55, and 56 are OR circuits. AND circuits 34-45 and OR circuits 49-54 constitute a select circuit 57 of holding circuits 30-33. I
When TRGA is turned on, the set signals ST1-4 of the buffers 30-33 are cyclically turned on by the T flip-flops.

ITRGA is synchronized with τi, and its differential signal ITRGE generates select signals ID1-4 for buffers 30-34, and the correspondence between the buffers synchronized with τs and the select signals ID1-4 synchronized with τi is performed. I,
Trigger processing is performed in synchronization with τi. Next, τi>
A time chart of τs/2 (in the fast case) is shown in FIG.

In FIG. 7, ITRGC is on, ITR
When GD is off, the τi trigger is enabled at the rising edge, and when ITRGC is off and ITRGD is on, the τi trigger is enabled at the falling edge. Next, τi>τ
A time chart of s/2 (slow case) is shown in FIG. In FIG. 8, the rising edge of ITRGB is delayed, but the τi trigger becomes valid at the rising edge and becomes valid at the falling edge, as in the above case.

Even when τs/2<τi<τs, there are times when it is fast and times when it is slow, and the respective time charts are shown in FIGS. 9 and 10. Also, even when τi≧τs, there are times when it is fast and times when it is slow, and the respective time charts are shown in Figures 11 and 1.
Shown in 2. In this embodiment, continuous τs triggers can also be converted to τi triggers at optimal timing.
Capable of high-speed data transfer.

[0026]

As described above, according to the present invention, the timing of transmitting the τi trigger is optimized by the period ratio of τs and τi, so that high-speed data transfer can be performed.

[Brief explanation of the drawing]

[Fig. 1] Diagram explaining the principle of the present invention

[Fig. 2] A diagram showing an embodiment of the present invention.

[Figure 3] Time chart for τi<τs/2

[Figure 4] τs
/2<τi<τs time chart

[Figure 5] τi≧τs
time chart of

FIG. 6 is a diagram showing another embodiment of the present invention.

[Figure 7] Time chart for τi<τs/2 (fast case)

[Figure 8] Time chart for τi<τs/2 (slow case)

[Figure 9] Time chart of τs/2<τi<τs (fast case)

[Figure 10] Time chart of τs/2<τi<τs (slow case)

[Figure 11] Time chart of τi≧τs (fast case)

[
Figure 12: Time chart of τi≧τs (slow case)

[Figure 13] Diagram showing a conventional example

[Figure 14] Time chart of conventional example

[Explanation of symbols]

11, 12: D flip-flop 13: Synchronization circuit 14: D flip-flop (differential circuit) 15: Switching circuit 16-18: AND circuit 19: D flip-flop 20: OR circuit 21-24: T flip-flop 25, 26 , 28, 29: T flip-flop 27: Exclusive OR circuit 30-33: Buffer (holding circuit) 34-45, 46-48: AND circuit 49-54, 55, 56: OR circuit 57: Select circuit

Claims (3)

[Claims] 1. A synchronization circuit (13) that synchronizes an input τs trigger with τi synchronization, a differentiation circuit (14) that takes the differential of the output of the synchronization circuit (13), and the differentiation circuit (14).
The timing to generate the τi trigger from the output of is τs and τ
An asynchronous trigger transmission circuit characterized by comprising a switching circuit (15) that switches according to a period ratio of i. 2. The switching circuit (15) is connected to the synchronization circuit (15).
2. The asynchronous trigger transmission circuit according to claim 1, wherein the asynchronous trigger transmission circuit switches between the leading edge differential of step 13), the output of the leading edge differential received by a one-stage flip-flop (19), and the trailing edge differential. 3. The switching circuit (15) includes a plurality of holding circuits (30 to 33) holding the τs trigger and the holding circuit (30 to 33) holding the τs trigger.
-33),
2. The asynchronous trigger transmission according to claim 1, wherein the τi trigger is enabled by turning on and off the synchronous output of the τs trigger and the differential output of its leading edge, and turning on and off the synchronous output and the differential output of its trailing edge. circuit.