JPH04282958A - Digital transmitter - Google Patents

Abstract

PURPOSE:To send a facsimile signal in 9600bps (nominal) through a digital transmission line of 9600bps (nominal) when the facsimile signal of a G3 facsimile equipment is sent through the digital transmission line. CONSTITUTION:A CPU 7 writes a facsimile signal (digital data) outputted from a MODEM 3 to a RAM 8 and detects an EOL in the facsimile signal. The data in the RAM 8 is read synchronously with the 9600Hz clock for a high speed digital line 9 and in order to compensate a frequency difference between the 9600Hz clock and a 9600Hz clock for the MODEM 3 (both the frequencies are nominal frequencies but they are seldom coincident with each other), a fill bit is inserted before the EOL in the data given to the high speed digital line 9.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital transmission device connected between a G3 facsimile machine and a digital transmission path for transmitting and receiving facsimile signals over the digital transmission path.

0002

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional digital transmission device along with its surroundings. In the figure, 1 is the International Telegraph and Telephone Consultative Committee (CCITT) Recommendation T. Group 3 (G3) facsimile device compliant with 30, 2 is the line through which the facsimile signal passes, 3 is the modem that modulates and demodulates the facsimile signal, 4 is the data transmission speed on the line 2 side and the high-speed digital line (digital transmission line) 9
5 is an oscillator; 6 is a frequency adjustment circuit that adjusts the frequency of the clock signal output from the oscillator 5;
11 is a digital transmission device.

Next, the operation will be explained. The facsimile signal sent by the G3 facsimile machine 1 is demodulated by the modem 3 and converted into digital data. The digital data is then sent to the high-speed digital line 9. For example, in the digital transmission device on the receiving side, the digital data received via the high-speed digital line 9 is turned into an analog signal by the modem 3, and the signal is supplied to the G3 facsimile machine 1 on the receiving side.

[0004] For example, even if the data transmission speed of the facsimile signal passing through the line 2 and the data transmission speed of the high-speed digital line 9 are the same, 9600 bps, strictly speaking, there is a difference between them. This is because the clock generation source of the synchronous clock in the G3 facsimile machine 1 and the clock generation source of the synchronous clock in the high-speed digital line 9 are different. Therefore, without any control, bit errors will occur. Therefore, the stack destuff circuit 4 is used to compensate for the speed difference.

That is, the stuff and destuff circuit 4 is as follows:
Information indicating the speed difference plus a synchronization signal is sent to the high-speed digital line 9 in addition to digital data in the form of a facsimile signal.

The stuff/destuff circuit 4 that receives digital data from the high-speed digital line 9 extracts a synchronization signal and information indicating a speed difference from the received signal, and passes the digital data excluding these to the modem 3. Also,
The frequency adjustment circuit 6 adjusts the oscillator 5 so as to generate a clock having the same frequency as the frequency of the synchronization clock of the G3 facsimile machine on the transmitting side, which can be determined from the speed difference. The modem 3 inputs the digital data output from the stuff/destuff circuit 4 in synchronization with the clock output from the oscillator 5, and provides a modulated wave for the digital data to the G3 facsimile machine 1 via the line 2.

[0007]

[Problems to be Solved by the Invention] Since the conventional digital transmission device is configured as described above, the 9600 bp
In order to transmit the facsimile signal of
It had to be faster than bps, and there was a problem in that the transmission path was wasted. In addition, as prior art related to digital transmission equipment capable of transmitting facsimile signals, Japanese Patent Application Laid-Open No. 62-47255 and Japanese Patent Application Laid-Open No. 63-23762
There is one shown in Publication No. 4.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a digital transmission device capable of transmitting a nominally 9600 bps facsimile signal over a nominally 9600 bps digital transmission line.

[0009]

[Means for Solving the Problems] A digital transmission device according to the present invention detects a synchronization code in a facsimile signal from digital data outputted by a modem, and determines the data transmission speed of the digital data outputted by the modem, such as fill bit. Compensation data that compensates for the difference in data transmission speed of digital data on the digital transmission path and does not affect the decoding operation of the G3 facsimile machine on the receiving side is inserted before the synchronization code, and the compensation data is inserted. The controller is equipped with a control section that sends the digital data that has been read to the digital transmission line.

0010

[Operation] The control unit in the present invention adjusts the data transmission speed of the facsimile signal output from the modem and the data on the digital transmission path by appropriately inserting compensation data such as fill bits into the facsimile signal passing through the digital transmission path. Compensate for speed differences in data transmission rates.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In Figure 1, 7 is a line synchronization code (hereinafter referred to as EO
It's called L. ) and insert fill bits.
PU (control unit); 8 is a RAM for temporarily storing digital data output from the modem 3; and 10 is a digital transmission device. Other parts are the same as those shown in FIG. 6 with the same reference numerals. Note that in this example, EO
L is used as a synchronization code and fill bits are used as compensation data.

Next, the operation will be explained. Figure 2 shows CCI
TT Recommendation T. 4 shows an example of the structure of a facsimile signal based on the one-dimensional encoding method defined in the Japanese Patent No. 4. In this configuration, the data (DATA) between two EOLs is 1
The data is for a line, and the number of bits of data for one line is according to recommendation T. When the number of bits corresponding to the minimum transmission time specified in Section 4 is not reached, one or more fill bits (FILL) are added so that the data between EOLs has the number of bits corresponding to the minimum transmission time.

FIG. 3 is a block diagram for explaining the operation of the CPU 7. In the figure, 13 is an EOL detection section (
Specifically, it is a program. ). CPU7 is
When digital data is received from modem 3, it is sent to RA
Write to M8. At this time, the actual data transmission rate is f
Suppose it was 1. The EOL detection unit 13 of the CPU 7
At the same time, EOL in the digital data is detected. Then, the EOL position is memorized.

Data in the RAM 8 is read out in synchronization with a 9600 Hz clock on the high speed digital line 9 side. At this time, the actual frequency of the 9600Hz clock is f0
Suppose it was. When f0 ≠ f1, some compensation processing is required, but when f1 < f0,
This can be compensated for by inserting a new fill bit before EOL. In this case, when the CPU 7 knows the difference between f0 and f1, it can know at what rate the fill bits should be inserted (for how many bits of digital data should one bit be inserted, etc.). In addition, the CPU 7
Since the data delay in M8 can be recognized, the read timing of the EOL detected by the EOL detection section 13 can also be known.

Therefore, the CPU 7 inhibits data output from the RAM 8 immediately before the EOL read timing closest to the timing at which the fill bit should be inserted. And 9
A fill bit is output in synchronization with a 600Hz clock. Thereafter, the RAM 8 is made readable again. In this way, a fill bit is inserted into the digital data sent to the high-speed digital line 9 to compensate for the speed difference.

Further, digital data received from the high-speed digital line 9 is provided to the modem 3 as is. In this case, a facsimile signal with appropriate fill bits added to the facsimile signal sent by the G3 facsimile machine on the transmitting side is given to the G3 facsimile machine on the receiving side, but the operation of the G3 facsimile machine There will be no problem.

Note that when the two-dimensional encoding method is executed in the G3 facsimile device 1, the structure of the facsimile signal becomes as shown in FIG. is the same as

[0018] Furthermore, when the G3 facsimile machine 1 equipped with an error correction mode transmits in that mode,
The facsimile signal is transmitted in an HDLC frame configuration. That is, the digital data output by the modem 3 periodically includes a flag pattern. Therefore,
As shown in FIG. 5, a flag detection section 14 is provided in place of the EOL detection section 13, and a flag pattern is inserted immediately before or after the flag pattern in the data output by the RAM 8 at a predetermined timing to compensate for the speed difference. It's okay. In this case, the flag pattern in the facsimile signal is used as a synchronization code, and the inserted flag pattern is used as a compensation bit.

[0019]

As described above, according to the present invention, a digital transmission device can be used to convert digital data sent to a digital transmission path into a data transmission speed that is equal to the data transmission speed of the digital data output by the modem and the data transmission speed on the digital transmission path. 9600 bps
This has the advantage of being able to transmit facsimile signals at 9600 bps over a digital transmission line.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a digital transmission device according to an embodiment of the present invention together with its surroundings.

FIG. 2 is an explanatory diagram showing an example of a configuration of a facsimile signal.

FIG. 3 is a block diagram for explaining the operation of a CPU.

FIG. 4 is a block diagram for explaining other operations of the CPU.

FIG. 5 is an explanatory diagram showing an example of a configuration of a facsimile signal.

FIG. 6 is a block diagram showing a conventional digital transmission device along with its surroundings.

[Explanation of symbols]

1 G3 facsimile machine 3 Modem 7 CPU (control unit) 8 RAM

Claims (1)

[Claims] 1. A modem that restores digital data from a signal received from a G3 facsimile machine and transmits a modulated wave created from the digital data to the G3 facsimile machine, and a synchronization code in the facsimile signal from the digital data output by the modem. detect,
G3 data on the receiving side that compensates for the difference between the data transmission speed of digital data output by the modem and the data transmission speed of digital data on the digital transmission path.
A digital transmission device comprising: a control unit that inserts compensation data that does not affect a decoding operation of a facsimile machine before the synchronization code, and sends digital data into which the compensation data has been inserted to the digital transmission path.