JPH04287253A - Parity check circuit - Google Patents

Abstract

PURPOSE:To analyze the cause of an error by providing a parity error inspection circuit, latch circuit, and I/O port. CONSTITUTION:The parity chec circuit is provided with the 1st random access memory 1 for storing write data, circuit 3 for generating the parity bit data of write data, and the 2nd random access memory 2 for storing the parity bit data. The circuit is also provided with a parity error detection circuit 4, latch circuit 5, and I/O port 6. The parity bit data outputted from the 2nd memory circuit 2 are held in the latch circuit 5 at the readout time. When a parity error occurs, the input and output data of the 1st memory 1 are compared with each other and, when both data are equal to each other, the parity bit data are read out the port 6 and combined with the data read out the memory 1. Therefore, whether the error is caused by the circuit 1 or detection circuit 4 can be discriminated.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity check circuit in a random access memory circuit used in a computer or the like.

0002

2. Description of the Related Art In recent years, computers have been widely used, and the reliability of data is checked by a parity check when data is exchanged in a random access memory circuit.

Hereinafter, the conventional parity check circuit includes a first random access memory circuit 1 that stores write data, and a parity bit generation circuit that receives the write data and generates parity bit data for detecting errors in the write data. 3, a second random access memory circuit 2 that stores the parity bit data, read data output from the first random access memory circuit 1 when reading the memory, and a second random access memory circuit 2 that stores the parity bit data. It is comprised of a parity error detection circuit 4 which receives the output parity bit data and detects the presence or absence of a parity error based on the read data and the parity bit data.

The operation of the above configuration will be explained. When data is written to the first random access memory circuit 1, the data is also input to the parity bit generation circuit 3,
Parity data is generated and written to the second random access memory circuit 2.

Next, when reading data from the first random access memory circuit 1, the read data output from the first random access memory circuit 1 and the parity output from the second random access memory circuit 2 are combined. The bit data is input to a parity error detection circuit 4, and the presence or absence of a parity error is detected.

[0006]

SUMMARY OF THE INVENTION In such a conventional parity check circuit, there are cases where a parity error is detected and it is desired to know the cause of its occurrence. At this time, the cause of the malfunction of the first random access memory circuit 1 can be easily determined by comparing the contents of the data written to the first random access memory circuit 1 and the data read from the first random access memory circuit 1. When the parity error is caused by a malfunction of the random access memory circuit 2 or a malfunction of the parity error detection circuit 4, there is a problem in that it is impossible to determine which malfunction caused the parity error.

SUMMARY OF THE INVENTION The present invention solves the above problems and aims to provide a parity check circuit that can accurately analyze the causes of parity errors.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a first random access memory circuit for storing write data, and a first random access memory circuit for storing write data and parity bit data for error detection by inputting the write data. A parity bit generation circuit that generates a parity bit, a second random access memory circuit that inputs and stores the parity bit data, and read data and parity bits that are output from the first and second random access memory circuits when reading the memory. a parity error detection circuit that inputs data and detects the presence or absence of a parity error; a latch circuit that holds parity bit data that is output from the second random access memory circuit when reading; A parity check circuit is provided with an I/O port for reading parity bit data.

[0009]

[Operation] In the above configuration, the present invention holds the parity bit data output from the second random access memory circuit in the latch circuit during reading, and when a parity error occurs, the write data of the first random access memory and the read data, and if they are equal and there is no malfunction in the first random access memory, the parity bit data is read from the I/O port by software, and the parity bit data is compared with the read data of the first random access memory. In combination, it is possible to determine whether the cause of the error is due to malfunction of the random access memory circuit.
Alternatively, it is determined whether the error is due to malfunction of the parity error detection circuit.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS A parity check circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of the configuration of a parity check circuit according to an embodiment of the present invention. In the figure, the parity check circuit according to the embodiment of the present invention is
A first random access memory circuit 1 that inputs and stores write data;
A parity bit generation circuit 3 generates parity bit data for error detection from the data, a second random access memory circuit 2 inputs and stores the generated parity bit data, and a first random access memory circuit 1. a parity error detection circuit 4 that detects the presence or absence of a parity error based on read data output when reading the memory and parity bit data output from the second random access memory circuit 2 when reading the memory; and a second random access memory. It is composed of a latch circuit 5 that holds parity bit data output from the circuit 2 when reading, and an I/O port 6 that reads the parity bit data held in the latch circuit 5.

The operation of the above configuration will be explained. When writing data, the write data is input to the first random access memory circuit 1 and stored therein, and is also input to the parity bit generation circuit 3, where parity bit data corresponding to the data is generated and the second random access memory circuit 1 stores the write data. is stored in the random access memory circuit 2 of.

Next, during the data read operation, the first random access memory circuit 1 is
At the same time, the parity bit data stored in the second random access memory circuit is read out. The read data and parity bit data are input to a parity error detection circuit 4 to detect the presence or absence of a parity error. Further, the parity bit data read from the second random access memory circuit 2 is held in the latch circuit 5. The held parity bit data can be read out from the I/O port 6 by software.

When a parity error is detected by the parity detection circuit 4, the cause is determined by the following operation. First, write data and read data to the first random access memory circuit 1 are compared. If both are equal, there is no malfunction in the first random access memory circuit, and therefore, the cause of the parity error is a malfunction in the second random access memory circuit 2 or a malfunction in the parity error detection circuit 4. It is assumed that At this time, the parity bit data held in the latch circuit 5 is read from the I/O port 6 by software, and the read data of the first random access memory circuit 1 and the parity bit data held in the latch circuit 5 are compared. By doing so, it is determined whether the cause of the parity error is due to a malfunction of the random access memory circuit 2 or a malfunction of the parity error detection circuit 4.

As described above, the parity check circuit according to the embodiment of the present invention includes a latch circuit that holds parity data output during a read operation, and an I/O port that is a means for reading out the held data by software. By using a parity check circuit that has a similar structure, it is possible to accurately analyze the cause of parity error occurrence, including the circuit that stores parity data.

[0015]

As is clear from the above embodiments, the present invention provides a first random access memory circuit that stores write data, and a parity circuit that receives the write data and generates parity bit data for error detection. a bit generation circuit; a second random access memory circuit that stores parity bit data output from the parity bit generation circuit; and read data output from the first and second random access memory circuits when reading the memory. a parity error detection circuit that inputs parity bit data and detects the presence or absence of a parity error; a latch circuit that holds parity bit data that is output from the second random access memory circuit when reading; and a latch circuit that holds the parity bit data that is output from the second random access memory circuit when read. By using a parity check circuit equipped with an I/O port for reading parity bit data, it is possible to accurately analyze the cause of a parity error.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a parity check circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a conventional parity check circuit.

[Explanation of symbols]

1 First random access memory circuit 2 Second random access memory circuit 3 Parity bit detection circuit 4 Parity error detection circuit 5 Latch circuit 6 I/O port

Claims (1)

[Claims] 1. A first random access memory circuit that stores write data; a parity bit generation circuit that receives the write data and generates parity bit data for error detection; and a first random access memory circuit that stores write data; a second random access memory circuit that stores parity bit data, and inputs the read data and parity bit data output from the first and second random access memory circuits when reading the memory, and checks the presence or absence of a parity error. A parity error detection circuit for detecting a parity error, a latch circuit for holding parity bit data output from the second random access memory circuit at the time of reading, and an I/O port for reading the parity bit data held in the latch circuit. parity check circuit.