JPH04287747A - Signal processing system - Google Patents

Abstract

PURPOSE:To provide a signal processing system capable of efficiently operating a microcomputer processing the conversion data from an A/D converter. CONSTITUTION:The first timer interruption routine Ia executed in response to the first interruption signal outputs an A/D conversion start command signal to an A/D converter and is completed without waiting the conversion work. The second timer interruption routine Ib executed in response to the second interruption signal is executed after the completion of the A/D conversion work and performs the calculation based on the digital conversion data. The period until the start of the second timer interruption routine Ib after the completion of the first timer interruption routine Ia is not spent to wait for the A/D conversion work, but it is spent for executing another program.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an A/D converter,
The present invention relates to a signal processing system including a microcomputer that processes digitally converted data from an A/D converter.

0002

[Prior Art] An airbag control system (signal processing system) disclosed in Utility Model Application Publication No. 2-5371 includes an acceleration sensor and an A/D converter that converts analog data representing acceleration from the acceleration sensor into digital data. It includes a converter, a microcomputer that processes digital conversion data from the A/D converter, and an airbag drive circuit controlled by the microcomputer.

The microcomputer described above executes a timer interrupt routine at regular intervals. In each timer interrupt routine, an A/D conversion start command signal is output to the A/D converter to convert analog data from the acceleration sensor into digital data, and after the conversion work is completed, calculations are performed based on this digital conversion data. In other words, the system integrates the acceleration represented by the converted data, and when the integrated value of acceleration in the deceleration direction exceeds a threshold level, it determines that a vehicle collision has occurred and outputs a trigger signal to the drive circuit to deploy the airbag. let

0004

[Problem to be Solved by the Invention] In the above microcomputer program, in each timer interrupt routine, the process from outputting an A/D conversion start command signal to the A/D converter to calculation based on digital conversion data is continued. In order to do this, it is necessary to wait for the conversion work in the A/D converter, and the execution time of the timer interrupt routine becomes longer by this waiting time, which shortens the execution time of other programs. In addition, if the conversion work in the A/D converter takes a long time, during the execution of the timer interrupt routine,
There is still the possibility that the next timer interrupt will occur and cause the microcomputer to run out of control.

[0005]

Means for Solving the Problems As shown in FIG. 1, a signal processing system according to the present invention includes an A/D converter 1 that converts analog data into digital data, and a microcomputer 2 that processes this digitally converted data. It is equipped with The microcomputer 2 includes a timer interrupt signal generating means 3 that alternately generates a first interrupt signal and a second interrupt signal, and an A/D converter that performs A/D conversion in response to the first interrupt signal. It includes first timer interrupt routine execution means 4 that outputs a start command signal, and second timer interrupt routine execution means 5 that performs calculations based on digital conversion data in response to the second interrupt signal. The time from the first interrupt signal generation point to the second interrupt signal generation point is the A/D
The time is set longer than the time required for A/D conversion work in the converter.

[0006]

[Operation] The first timer interrupt routine executed in response to the first interrupt signal outputs an A/D conversion start command signal to the A/D converter, but ends without waiting for the conversion operation. A second timer interrupt routine executed in response to the second interrupt signal is executed after the A/D conversion operation is completed, and performs calculations based on the digital conversion data. Therefore, the time from the end of the first timer interrupt routine until the start of the second timer interrupt routine is not spent waiting for A/D conversion work, but is spent running other programs. , the microcomputer can be operated efficiently.

[0007]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 2 to 4. FIG. 2 schematically shows a control system that controls squib S of an airbag (vehicle safety device). The control system includes an acceleration sensor 10 that outputs analog data representing acceleration in the acceleration direction and deceleration direction of the vehicle, and an A/D converter (analog-to-digital converter) 20 that converts the analog data from the acceleration sensor 10 into digital data. , a microcomputer 30 that processes digital conversion data from the A/D converter 20, and a drive circuit 40 for the squib S controlled by the microcomputer 30.

The drive circuit 40 includes a transistor 41 whose emitter is grounded, and a squib S is connected between the collector of the transistor 41 and the battery VB. The transistor 41 turns on when its base receives a high-level trigger signal from the microcomputer 30, ignites the squib S and deploys the airbag.

As shown in FIG. 3, the microcomputer 30 sends an A/D conversion start command signal to the A/D converter 2.
a first timer interrupt routine Ia for outputting to 0;
The second timer interrupt routine Ib for executing the acceleration evaluation program is executed at alternate intervals. The first timer interrupt routine Ia is very short, approximately 5 μs, because it ends without waiting for A/D conversion work. The second timer interrupt routine Ib is the first timer interrupt routine Ia.
The process starts after a time T1, for example, 100 μs after the start time. Since this time T1 is longer than the maximum time required for the A/D conversion work, the A/D conversion work has already been completed when the second timer interrupt routine Ib is started. The second timer interrupt routine Ib requires, for example, 250 μs, so from the start of the second timer interrupt routine Ib,
Time T2 until the start of the next first timer interrupt routine Ia
is set to, for example, 400 μs. As a result, sampling of the acceleration signal is executed at a cycle of T = T1 + T2 = 500 μs, and the evaluation program is also approximately 500 μs.
It is executed at the cycle of

Conventionally, the time from the end of the first timer interrupt routine Ia to the start of the second timer interrupt routine Ib is determined by the A/D converter 20 in the timer interrupt routine.
However, with the present invention, other programs can be executed in the main routine. As a result, the microcomputer 30 can be operated efficiently. Also, the first timer interrupt routine Ia is A/
Since it does not include the time for waiting for the D conversion work and is completed in a substantially constant and very short time, it does not overlap with the next second timer interrupt routine Ib. Therefore, it is possible to prevent the microcomputer from running out of control.

The microcomputer 30 executes the first timer interrupt routine Ia and the second timer interrupt routine Ib described above by using one output compare and an A/D conversion request flag. In detail,
The timer interrupt routine of FIG. 4 is executed in response to an interrupt signal from the output compare. The illustrated timer interrupt routine includes the first timer interrupt routine Ia and the second timer interrupt routine Ia.
It substantially includes a timer interrupt routine Ib.

First, it is determined whether the A/D conversion request flag is set (step 100). When the determination is affirmative, a command signal to start A/D conversion is sent to the A/D converter (step 101). Next, set the next interrupt to T1
The A/D conversion request flag is cleared (step 103), and the process returns to the main routine. These steps 100 to 103 constitute the first timer interrupt routine Ia described above. The scheduled interrupt time T1 is set by storing the value obtained by adding T1 to the current free running counter value in the output compare register. Although 2 to 3 μs elapse from the start of the interrupt to the time when the scheduled interrupt time T1 is actually set, this specification will ignore this time in the description.

[0013] The A/D converter 20 performs step 101.
In response to the A/D conversion start command signal output from
Start D conversion. When the conversion work in the A/D converter 20 is completed, the digital conversion data is stored in the dedicated register of the microcomputer 30, and the A/D converter 20
The D conversion end flag is set. Note that this A/D conversion end flag is cleared at the start of the next A/D conversion.

In the output comparison, when the value of the free running counter reaches the set value stored in the register, that is, when T1 has elapsed from the first timer interrupt routine Ia, an interrupt signal (second interrupt signal ) is output. In response to this interrupt signal, the next timer interrupt routine is executed. In this routine, step 100
will be judged negative. This is because the A/D conversion request flag was cleared in step 103 of the previous timer interrupt routine. Therefore, the process proceeds to step 104, and the next interrupt is set after T2 (step 10
4). The method of setting the scheduled interruption time T2 is the same as that for the scheduled interruption time T1.

Next, it is determined whether the A/D conversion end flag is set (step 105). If the judgment is affirmative, that is, if it is judged that the A/D converter 20 is normal, the acceleration evaluation program is executed (
Step 106). Specifically, the acceleration integral value is updated by adding the acceleration stored in the dedicated register to the previously determined acceleration integral value. and,
This updated acceleration integral value is compared with a threshold level. When the acceleration integral increases in the deceleration direction and exceeds the threshold level, it is determined that a vehicle collision has occurred and a trigger signal is output to the transistor 41 to deploy the airbag.

[0016] If a negative determination is made in step 105 above,
That is, if it is determined that the A/D conversion has not been completed, an NG flag indicating a failure of the A/D converter 20 is set (step 107). After executing step 106 or step 107, the A/D conversion request flag is set (step 108), and the process returns to the main routine. As is clear from the above description, steps 100, 10
4 to 108 execute the second timer interrupt routine Ib. Note that when the NG flag is set, a warning lamp (not shown) is turned on in the main routine.

When an interrupt signal (first interrupt signal) is output from the output compare after T2 has elapsed from the start of the second timer interrupt, the timer interrupt routine of FIG. 4 is executed again. In this case, since the A/D conversion request flag was set in step 108 of the previous second timer interrupt routine, steps 101 to 103, that is, the first timer interrupt routine Ia, are executed again.

FIGS. 5-7 show other embodiments of the invention. In this embodiment, analog data from the acceleration sensor 10 and other analog data, such as the voltage at one terminal of the squib S, are also input to the A/D converter 20 (see FIG. 2). A weak current is flowing through the squib S, and the terminal voltage varies depending on whether the squib S is normal or disconnected. As shown in FIG. 5, in this embodiment, when the A/D conversion work of acceleration data is completed, the A/D conversion of squib terminal voltage data is
A/D interrupt routine Ix is executed to initiate the /D conversion. That is, the first timer interrupt routine Ia for outputting the A/D conversion start command signal of acceleration data.
' and the second timer interrupt routine Ib' for the acceleration evaluation program, the A/D interrupt routine Ix is executed. The scheduled interrupt time T1' set in the first timer interrupt routine Ia' is the A/D of the acceleration signal.
This is longer than the total time required for conversion and A/D conversion of the squib terminal voltage. Furthermore, the scheduled interrupt time T2' set in the second timer interrupt routine Ib' is shown in FIG.
, shorter than the scheduled interrupt time T2 of the embodiment of FIG. The acceleration sampling cycle T' is equal to the cycle T of the embodiments of FIGS. 3 and 4. The A/D interrupt routine Ix ends in a very short time like the first timer interrupt routine Ia'.

In this embodiment, steps 100, 101, 102', 1 in the timer interrupt routine of FIG.
03,200 constitutes the first timer interrupt routine Ia'. Also, steps 100, 104', 105, 2
01, 106, 107, and 108 constitute the second timer interrupt routine Ib'. In step 200 after step 103, an A/D interrupt request flag is set. As a result, when the A/D conversion work of acceleration data is completed and the A/D conversion completion flag is set, the A/D conversion work is immediately performed.
The D interrupt routine Ix is executed. Further, in step 201 after step 105, the squib terminal voltage data whose conversion was started in the A/D interrupt routine Ix before the second timer interrupt routine Ib' is transferred from the dedicated register to the dedicated RAM. and saved. As a result, the first timer interrupt routine after this second timer interrupt routine Ib'
When the acceleration data whose conversion is started in the timer interrupt routine Ia' enters the dedicated register, the squib terminal voltage data does not disappear.

In the A/D interrupt routine Ix, as shown in FIG. 6, the acceleration data converted before the A/D interrupt routine Ix is transferred from the dedicated register to the dedicated RAM.
and save it (step 300). This results in
When the squib terminal voltage data whose conversion is started by this A/D interrupt routine Ix enters the dedicated register, the acceleration data will not disappear. Next, the squib terminal voltage A
/D conversion start command signal is output (step 301),
Clear the /D interrupt request flag (step 302).

[0021]

[Effects of the Invention] As explained above, in the present invention, A/
A/D
The time is not spent waiting for conversion work, but is used for executing other programs, allowing the microcomputer to operate more efficiently. Furthermore, since there is no interference between timer interrupt routines, it is possible to reliably prevent the microcomputer from running out of control.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of a control system of the present invention.

FIG. 2 is a circuit diagram schematically showing an embodiment of a control system according to the present invention.

FIG. 3 is a time chart of a timer interrupt routine executed by the microcomputer in FIG. 2;

FIG. 4 is a flowchart showing the timer interrupt routine of FIG. 3;

FIG. 5 is a time chart when the microcomputer executes a timer interrupt routine and an A/D interrupt routine.

FIG. 6 is a flowchart showing a timer interrupt routine in the time chart of FIG. 5;

FIG. 7 is a flowchart showing an A/D interrupt routine in the time chart of FIG. 5;

[Explanation of symbols]

1,20 A/D converter

Claims (1)

[Claims] 1. A signal processing system comprising: an A/D converter that converts analog data into digital data; and a microcomputer that processes digitally converted data from the A/D converter; a timer interrupt signal generating means that alternately generates an interrupt signal and a second interrupt signal; and a first timer that outputs an A/D conversion start command signal to the A/D converter in response to the first interrupt signal. The second timer interrupt routine execution means includes an interrupt routine execution means and a second timer interrupt routine execution means for performing an operation based on digital conversion data in response to the second interrupt signal, and generates the second interrupt signal from the time when the first interrupt signal is generated. The time up to the point is
A signal processing system characterized in that the time is set longer than the time required for A/D conversion work in an A/D converter.