JPH04290233A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To relax a concentration gradient with reference to an adjacent outer base and to weaken the electrolytic intensity inside a depletion layer of an emitter-base junction face by a method wherein a low-concentration emitter is formed at the outer circumference of a high-concentration emitter to be used as an intrinsic emitter. CONSTITUTION:A silicon oxide film 8 and a silicon nitride film 9 are formed on a semiconductor substrate 1 where an outer base 6 and an intrinsic base 7 have been formed. An opening which is wider than an emitter contact 10 is formed in the silicon nitride film 9; the emitter contact 10 is formed in the silicon oxide film 8; polysilicon 11 with which the emitter contact 10 is covered is formed; after that, N-type impurities are ion-implanted; low-concentration emitters 12, 13 and, at the same time, a high-concentration emitter 14 are formed. At this time, the surface concentration of the low-concentration emitters 12, 13 is adjusted to 1/10 to 1/100 of the surface concentration of the high- concentration emitter 14 in such a way that it is the same as the surface concentration of the intrinsic base 7.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing bipolar integrated circuits.

0002

[Prior Art] A method of manufacturing a bipolar integrated circuit according to the prior art is shown in FIGS. 3(a) to 3(c) and FIG. 4(a).
This will be explained with reference to (c).

First, as shown in FIG. 3(a), an N-type buried layer 2 in which arsenic or antimony is diffused is formed in a device area of a P-type semiconductor substrate 1, and then an N-type epitaxial layer 3 is grown. Next, a silicon oxide film 4 for insulation isolation is formed by the LOCOS selective oxidation method, and a collector extraction layer 5 connected to the N-type buried layer 2 is formed by diffusing phosphorus or the like.

Next, as shown in FIG. 3(b), using a resist (not shown) as a mask, a P-type impurity such as boron is implanted at an acceleration energy of 10 to 30 keV and an implantation amount (dose) of 1×.
After ion implantation of 1015~1×1016 cm-2,
The external base 6 is formed by annealing at 900 to 1000° C. for several tens of minutes in a nitrogen atmosphere.

At this time, the surface concentration of the external base 6 formed near the emitter is 1×10 19 cm −3 or more,
It has the role of drawing electricity from the intrinsic base directly under the emitter to the surface of the element with low resistance.

Next, as shown in FIG. 3(c), the intrinsic base 7 is formed by ion-implanting a P-type impurity such as boron at a dose of 1×10 13 to 1×10 14 cm −2 at a low energy of 30 keV or less. Form.

Next, as shown in FIG. 4(a), after opening the emitter contact 10, a thickness of 1000 to 2000 mm is formed.
Polysilicon 11 of A is grown. Next, an N-type impurity such as arsenic is introduced into the polysilicon 11 by high-dose ion implantation of 1.times.10@16 cm@-2 or more.

Next, as shown in FIG. 4B, polysilicon 11 is covered with a CVD silicon oxide film 12, and then heat treatment is performed at 900 to 1000° C. for several tens of minutes in a nitrogen atmosphere to remove N in polysilicon 11. Emitter 14 is formed by introducing type impurities into semiconductor substrate 1 .

If high performance is not particularly required or the junction of the diffusion layer does not need to be made shallow, the emitter 14 is formed by ion-implanting N-type impurities using a resist as a mask without growing the polysilicon 11. There are things to do.

Next, as shown in FIG. 4C, the CVD silicon oxide film 12 is removed and the polysilicon 11 is selectively etched to form an emitter electrode.

[0011]

In a conventional bipolar integrated circuit, an extrinsic base made of a heavily doped P-type diffusion layer is formed on the side surface of an N-type emitter for electrically drawing out the intrinsic base with low resistance.

[0012] Since the N-type emitter and the P-type external base are close to each other at the surface, leakage current between the junctions due to a voltage applied in the emitter-base reverse direction increases.

[0013] Therefore, the permissible limit of the voltage applied in the emitter-base reverse direction of the NPN type bipolar integrated circuit has to be kept low.

[0014]

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes the steps of forming a first insulating film on one main surface of a semiconductor substrate, and forming a second insulating film on the first insulating film. a step of selectively etching the second insulating film to form an opening wider than the emitter; a step of selectively etching the first insulating film to open an emitter contact; a step of depositing silicon to bury the emitter contact; a step of selectively etching the polysilicon leaving only the vicinity of the emitter contact; and ion implantation of N-type impurities to form an opening in the second insulating film. introducing the N-type impurity into the first insulating film and the polysilicon exposed to the polysilicon, and simultaneously introducing the N-type impurity in the polysilicon from the emitter contact into the semiconductor substrate by heat treatment; A bipolar transistor is formed from the step of activating the N-type impurity introduced into the semiconductor substrate through the first insulating film.

[0015]

[Example] Regarding an example of the present invention, FIGS. 1(a) to (
c) and FIGS. 2(a) to 2(c).

First, as shown in FIG. 1(a), an N-type buried layer 2 is formed on a P-type semiconductor substrate 1, an N-type epitaxial layer 3 is grown, and a silicon oxide film 4 is formed by the LOCOS selective oxidation method. do. Next, a collector extraction layer 5 connected to the N-type buried layer 2 is formed, and an extrinsic base 6 and an intrinsic base 7 are formed.

Next, as shown in FIG. 1(b), a silicon oxide film 8 with a thickness of 500 to 1000 Å is grown by a thermal oxidation method, and then a silicon oxide film 8 with a thickness of 1000 to 2000 Å is grown by a CVD method.
A silicon nitride film 9 is grown.

Next, as shown in FIG. 1(c), CF4
The silicon nitride film 9 is etched by chemical dry etching using gas to form an opening wider than the emitter contact.

Next, as shown in FIG. 2A, the silicon oxide film 8 is etched using buffered hydrofluoric acid using a resist (not shown) as a mask to open an emitter contact 10. Next, the thickness is 1000~ by CVD method.
Grow 2000A polysilicon 11 to fill emitter contact 10.

Next, as shown in FIG. 2B, the polysilicon 11 is anisotropically etched by RIE or the like, leaving the opening 0.2 μm wider on each side than the opening of the emitter contact 10.

Here, an N-type impurity such as arsenic is added at 1×101
By implanting high-dose ions of 6 cm-2 or more,
N-type impurities are introduced from the openings in the silicon nitride film 9 on both sides of the polysilicon 11 through the silicon oxide film 8,
Low concentration emitters 12, 13 are formed.

Next, as shown in FIG. 2C, heat treatment is performed at 900 to 1000° C. in a nitrogen atmosphere to diffuse N-type impurities from polysilicon 11 and form high concentration emitter 14. At the same time, low concentration emitter 12,1
The N-type impurity of No. 3 is activated, diffuses within the substrate 1, and overlaps with the high concentration emitter 14.

At this time, the surface concentration of the low concentration emitters 12 and 13 is made equal to the surface concentration of the intrinsic base 7.
1/10 to 1/100 of the surface concentration of the high concentration emitter 14
Adjust to.

[0024]

[Effects of the Invention] By forming a low concentration emitter on the outer periphery of a high concentration emitter which becomes an intrinsic emitter, it was possible to alleviate the concentration gradient with the adjacent external base.

As a result, it was possible to weaken the electric field strength within the depletion layer at the emitter-base junction. Leakage current due to reverse applied voltage between the emitter and base is reduced, making it possible to increase the allowable reverse applied voltage value.

The lightly doped N-type diffusion layer introduced into the outer periphery of the emitter only compensates for the heavily doped P-type impurity near the surface of the base layer, and does not affect the forward characteristics of the emitter-base.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing an embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing a method of manufacturing a bipolar integrated circuit according to the prior art in order of steps;

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a bipolar integrated circuit according to the prior art in order of steps.

[Explanation of symbols]

1 P-type semiconductor substrate 2 N-type buried layer 3 N-type epitaxial layer 4 Silicon oxide film 5 Collector drawer layer 6 External base 7 Intrinsic base 8 Silicon oxide film 9 Silicon nitride film 10 Emitter contact 11 Polysilicon 12, 13 Low concentration emitter 14 High concentration emitter

Claims (1)

[Claims] 1. A step of forming a first insulating film on one main surface of a semiconductor substrate, a step of forming a second insulating film on the first insulating film, and selecting the second insulating film. etching to form an opening wider than the emitter;
a step of selectively etching the insulating film of to open an emitter contact; a step of depositing polysilicon on the entire surface to bury the emitter contact; and selectively etching the polysilicon leaving only the vicinity of the emitter contact. a step of ion-implanting an N-type impurity to introduce the N-type impurity into the first insulating film and the polysilicon exposed in the opening of the second insulating film;
introducing the N-type impurity in the polysilicon from the emitter contact into the semiconductor substrate by heat treatment, and simultaneously activating the N-type impurity introduced into the semiconductor substrate through the first insulating film; A method for manufacturing a semiconductor device forming a transistor.