JPH0429073B2 - - Google Patents

Description

[Detailed description of the invention]

"Field of Industrial Application" The present invention relates to a display controller used in a color display device or the like controlled by a CPU (Central Processing Unit). ``Prior Art'' In CPU-controlled color display devices, blinking (flickering) display is often used to improve the display effect. To perform this blinking display, display data (color code) in VRAM (video RAM) can be rewritten at regular intervals, but this method has the problem of placing a heavy burden on the CPU. Therefore, a display device is known in which two registers are provided in the display controller in advance, data is written in the registers, and the data in the registers are alternately used to perform a blink display. "Problems to be Solved by the Invention" However, in the conventional blinking display, the display color during blinking is determined by data in two registers, and in order to change this display color, The data in the register had to be changed. Therefore, an object of the present invention is to provide a display controller that can change the display color during blinking without changing the data in the register. "Means for Solving the Problem" This invention provides first and second registers into which color change data for changing color data is written, and the color change data written in the first and second registers. a first selection means that alternately outputs at a predetermined timing, and outputs bit designation data that specifies which bit of the output of the first selection means is to be replaced with a corresponding bit of the color data. a third register to
A second color code that replaces a plurality of bits specified by the bit designation data with corresponding bits of the color code among the color change data output by the first selection means and outputs the color code as a new color code. It is characterized by comprising a selection means and a conversion means for converting the new color code outputted by the second selection means into the color data. "Embodiment" Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a color display device with dot display using a display controller 1 according to an embodiment of the present invention. This display device will be described in detail below. (1) General configuration In Figure 1, 2 is a CPU, 3 is a memory consisting of a ROM that stores programs used by the CPU 2, and a RAM for data storage, 4 is a video display processor (hereinafter referred to as VDP), 5 is VRAM. VDP4 is CPU2
The color code supplied via the bus line 6 is written into the VRAM5, the written color code is read out, and the dot data DD7-
It is sequentially output to the display controller 1 as 0 (8 bits). In addition, this VDP4 has a synchronization signal
SYN.I, blanking signal BLANK, display timing signal DTMG, page select signal PG-SEL and dot clock DCLK are output to the display controller 1, respectively. Here, the synchronization signal SYN・I is a signal for synchronizing the display on the CRT display device, and a blanking signal.
BLANK is a signal that is "1" during the screen display period and "0" during other periods, and the display timing signal DTMG is a signal that is "1" during the image display period and "0" during other periods. Note that the screen display period and the image display period are different. That is, the display screen is divided into an image display area and a border area, the image is displayed only in the image display area, and the border area is displayed in one color. The image display period is a period during which the image display area is scanned, and the screen display period is a period during which the screen (image display area and border area) is scanned. In addition, the page select signal PG-SEL is a signal that repeats "1" for 0.5 seconds and "0" for 0.5 seconds, for example.
The dot clock DCLK is a signal indicating the timing of displaying each dot on the display screen. The interface circuit 7 is a circuit for connecting the CPU 2 and the display controller 1. The display controller 1 receives dot data DD7 supplied from the VDP4.
-0 into R, G, B color data, and then convert these color data into red color signals RS,
Green color signal GS, blue color signal BS
(both are analog signals) and output to the CRT display device 8. Also, this display controller 1
outputs the signal YS and the synchronizing signals SYN and O to the CRT display device 8. Note that in this controller 1, the terminal T1 is directly connected to the data bus of the CPU 2. The CRT display device 8 is a color display device that has the function of a television receiver, and the CRT display device 8 is a color display device that has the function of a television receiver.
When is “1”, the red color signal RS, green color signal GS,
Color display is performed based on the blue color signal BS and the synchronization signal SYN/O, and when the signal YS is "0", the display is performed using a television signal. (2) Detailed configuration of display controller 1 FIGS. 2 to 4 are circuit diagrams each showing a detailed configuration of display controller 1. This display controller 1 can be roughly divided into a control section shown in FIG.
It is divided into a RAM address forming section shown in FIG. 3, and a dual port RAM 11 and color data modification circuits 12r, 12g, and 12b shown in FIG. The configuration of each part will be explained below. Note that the operation of each part will be explained in detail later. (2-1) Control unit; FIG. 2 This control unit is a circuit that mainly controls data exchange between the CPU 2 and the display controller 1. In the figure, 17 is a 3-bit register, which reads input data based on the dot clock DCLK supplied to its load terminal L, and outputs it from its output terminal. This register 17 is a register for synchronization. That is, the clock pulse of the CPU 2 and the dot clock DCLK output from the VDP 4 are not synchronized. Therefore, for signals and data synchronized with the clock pulse of CPU2, the dot clock DCLK
signals and data that are synchronized with Register 17 is provided for this purpose. Also, the DF shown below the same register 17
(D-type flip-flop) 18 is also provided for this purpose. The pointer counter 19 is 4
It is a bit up counter and its up terminal
Up-counts the signal supplied to UP, and also
Data WD3 when signal is supplied to load terminal L
Read -0. Note that data WD3-0 is the lower four bits of the output of the register 60 shown at the bottom of the figure. The write decoder 20 decodes the output of the pointer counter 19, becomes enabled only when the write strobe WRST is supplied to its enable terminal EN, and outputs the decoding result as a strobe signal S|MW, . Similarly, the read decoder 21 decodes the output of the pointer counter 19, and outputs the decoding result as a strobe signal S|MR only when the read strobe RDST is supplied. 21 and 22 are buffers, and when a "1" signal is supplied to the control terminal C, the input data is output as is from the output terminal, and when a "0" signal is supplied, the output terminal becomes high impedance. state. Further, the line connecting the buffer 27 and the terminal T1 is an 8-bit bidirectional bus. When the signal CS is supplied to the load terminal L of the register 60, the terminal T1
The data obtained from the CPU 2, that is, the data on the data bus of the CPU 2, is read and output to the register 24. Register 24 is the write strobe WRST
When supplied, the output data of the register 23 is read and output as data WDB7-0. The mode register 25 receives data WD5-0 (data WDB7-0) when the strobe signal S|MD is supplied.
This is a 6-bit register that reads the lower 6 bits of (2-2) RAM address forming unit; Figure 3 This RAM address forming unit includes a block B1 that converts dot data (color code) DD7-0 to new dot data DDa7-0,
Address data RWA7-0 (8 bits) and
Block B2 forming BA1-0 (2 bits)
Each data is divided into dual ports.
Address terminals AT2, AT of RAM11 (Figure 4)
1 (AT1, AT1-0). In block B1, 30 and 31 are each 4-bit page registers, and 32 is a multiplexer. The multiplexer 32 outputs the data at the input terminal <1> when a "1" signal is supplied to its control terminal C, and outputs the data at the input terminal <0> when a "0" signal is supplied. do. 33 is a synchronization register, 34 is a 4-bit page mask register,
35 is a synchronization register, and 36 to 39 are multiplexers. Also, in block B2, 41
is a synchronization register, 42 is a multiplexer, 43
is a word counter, and 44 is a byte counter. These counters 43 and 44 each output data WDB7- when a signal is supplied to the load terminal L.
0, WDB1-0 is read, and when a “1” signal is supplied to the enable terminal EN,
Outputs the signal from the up terminal UP. Also,
A carry-out signal CO of the byte counter 44 is supplied to an input terminal of an OR gate 45. (2-3) Dual port RAM 11; Figures 4 and 5 This dual port RAM 11 is a LUT that converts color codes into color data, and has 1024
It consists of a byte RAM 11a and peripheral circuits. FIG. 5 is a diagram showing the configuration of the RAM 11a, and addresses 0 to 3 of this RAM 11a each have
R, G, B color data and attribute bits (8 bits each) corresponding to color code "0" are stored, and R, G, B colors corresponding to color code "1" are stored in addresses 4 to 7. Data and attribute bits are stored, ..., 1020 ~
At address 1023, R, G, and B color data and attribute bits each corresponding to the color code "255" are stored. Then, based on the dot data DDa7-0 (color code) supplied to the address terminal AT2 of the dual port RAM 11, the corresponding R, G, B color data and attribute bits are read out, and the R, G, B
Color data is output as color data RD7-0, GD7-0, BD7-0 from output terminals Q2 to Q4, respectively, and attribute bits are output from output terminal Q5. In this case, the seventh and sixth bits of the attribute bits are output as attribute data AD7 and AD6. In addition,
Bits 5 to 0 of the attribute bits are not used in this embodiment. Further, the function of the attribute bit will be explained later. In this way, the dual port shown in Figure 4
When dot data DDa7-0 is applied to the address terminal AT2, the RAM11 responds to R, G,
B color data and attribute bits are read out, but completely independent of this readout,
Writing/reading of the RAM 11a can be performed in byte units. That is, by applying address data (10 bits) to the address terminal AT1 of this dual port RAM 11, applying 8-bit data to the data terminal WDT, and applying a pulse signal to the write terminal WT, writing to the RAM 11a can be performed. done,
Furthermore, by applying address data to the address terminal AT1 and applying a pulse signal to the read terminal RT, data within the address indicated by the address data is read out and output from the output terminal Q1. Address data RWA7-0 and
BA1-0 is data that specifies the address for reading/writing as described above, and address data RWA7-0 is the upper 8 of the address terminal AT1.
Address data BA1-0 is applied to the lower two bits, respectively. (2-4) Color data modification circuit 12r, 12g,
12b; FIG. 4 These color data modification circuits 12r to 12b have the same configuration, and color data RD7
-0, GD7-0, BD7-0 are modified according to the attribute signal AS, then the modified data is converted to an analog signal, and the color signals RS,
Output as GS, BS. The attribute signal AS is a signal obtained by delaying the attribute data AD7 by one dot clock timing (hereinafter simply referred to as timing) by the register 46. Next, in the color data modification circuit 12r,
47r is a register that outputs color data RD7-0 with one timing delay, and 48r is the above signal.
Multiplexer controlled by AS, 49r
is an adder circuit, and 50r is a border register into which color data for determining the color of the border area is written. 51r is a multiplexer, 52r is a register that delays the output of the multiplexer 51r by one timing, 53r is a buffer, and 56r is a gate circuit. This gate circuit 54r becomes open when a "1" signal is applied to its control terminal C, and becomes closed when a "0" signal is applied. 55r is DAC
(digital/analog converter), and this
The output of the DAC 55r is output as a color signal RS via an amplifier 56r. (3) Operation of display controller 1 (3-1) Operation during writing by CPU 2 Prior to display processing, CPU 2 controls each register and dual port in display controller 1.
Write data to RAM11. During this writing, a strobe signal is output from the write decoder 20 (FIG. 2). Further, a register number is assigned to each register. The relationship between the register number, the strobe signal, the register to which writing is performed, etc. is as follows. 0 S|MW...Dual port RAM 11 1 S|MD...Mode register 25 (Fig. 2) 2 S|WA...Word counter 43 (Fig. 3) 3 S|BA...Byte counter 44 (Fig. 3) ) 4 S|MA...Page mask register 34 (3rd
(Figure) 5 S|P0...Page register 30 (Figure 3) 6 S|P1...Page register 31 (Figure 3) 7 S|BR...Border register 50r (Figure 4) 8 S|BG... Border register 50g (FIG. 4) 9 S|BB...Border register 50b (FIG. 4) Next, the operation at the time of writing will be explained. Note that two addresses are assigned to the interface (FIG. 1) as port addresses. Hereinafter, these addresses will be referred to as port addresses PA0 and PA1. (i) Register individual write operation This operation is performed by registers 25, 43,...
This is an operation when writing data to any one of the 50b. In this case, the CPU 2 first outputs the port address PA0 to the address bus, then outputs the register number to the data bus, and then outputs a write pulse (hereinafter referred to as the first process). When the port address PA0 is output, the interface 7 detects this and outputs "0" as the signal AO. Next, when the write pulse is output, the interface 7 outputs "1" as the read/write signal WR and also outputs the pulse signal CS at the same timing as the write pulse. When the pulse signal CS is output from the interface 7, this signal CS is sent to the register 60.
(Figure) is supplied to the load terminal L, thereby,
The register number on the data bus is read into register 60 and supplied to the input end of pointer counter 19. On the other hand, when the signal AO becomes "0" and the signal WR becomes "1", the AND gate 61 (FIG. 2) becomes open, and the pulse signal CS passes through the AND gate 61 and the synchronization register 17 to the pointer counter 19. is applied to the load terminal L of. As a result, the register number read into the register 60 is read into the pointer counter 19 and output to the write decoder 20. Next, the CPU 2 outputs the port address PA1 to the address bus, then outputs write data to the data bus, and then outputs a write pulse (hereinafter referred to as second processing). Interface 7 receives port address PA1 and outputs signal AO.
In response to a write pulse, it outputs "1" as a read/write signal WR and outputs a pulse signal CS. When the pulse signal CS is output, data on the data bus is read into the register 60. Also, the signal
When AO and WR become “1”, AND gate 62
is in the open state, and the signal CS is the AND gate 62,
Write strobe via register 17
Output as WRST. This write strobe WRST causes the data in the register 60 to be read into the register 24, and this read data is supplied to the registers 25, 43, . . . . Also, when the write strobe WRST is output,
While this strobe WRST is being output, the write decoder 20 is enabled, and the strobe signal S|MW corresponding to the output of the pointer counter 19 is output from the write decoder 20. As a result, the data in the register 24 is read into the registers 25, 43, . . . to which the same strobe signal is applied. (ii) Register continuous write operation This operation is an operation when data is continuously written into a plurality of registers 25, 43, . . . . In this case, the CPU 2 first stores the first value in the mode register 25 (FIG. 2) by the process described in (i) above.
Write data that makes the bit “1”. As a result, the signal AUT output from the same register 25
-INC becomes "1", this "1" signal is supplied to the AND gate 63 (upper left in FIG. 2), and the AND gate 63 becomes open. Next, for example, each register 34, 30 with register numbers "4" to "9"...
When writing data to the register 50b, the CPU 2 writes the data into the register 34 with register number "4" by performing the process (i) above. When this writing is completed, the register number "4" is held in the pointer counter 19. Next, the CPU 2 performs the second process in the process (i) above, that is, outputs the port address PA1, outputs the data to be written to the register 30 with register number "5", and outputs a write pulse. As a result, "1" is output from the interface 7 as the signals AO and WR, and the pulse signal CS is output, and the above data is transferred to the register 60 by the pulse signal CS.
is loaded into. Then light strobe
WRST is output and this light strobe
The data in register 60 is read into register 24 by WRST. Also, the write strobe WRST is sent to the pointer counter 1 via the OR gate 64, the AND gate 63, and the register 17.
As a result, the pointer counter 19 is incremented, its count output becomes "5", and this count output "5" is supplied to the write decoder 20. As a result, the strobe signal S|P0 is output from the write decoder 20 at the timing of the write strobe WRST, and the data in the register 24 is transferred to the register 30 (FIG. 2) by this strobe signal S|P0.
loaded within. Similarly, when the CPU 2 sequentially outputs data to be written into the registers 31, 50r, 50g, and 50b by the second process, these data are sequentially written into each register. (iii) RAM individual write operation This operation is for writing data only into any one address of the RAM 11a.
In this case, the CPU 2 first writes "0" to the fifth bit of the mode register 25. As a result, the signal DIF-RD becomes "0". When the signal DIR-RD becomes “0”, the multiplexer 42 (Fig. 3)
The data at the input terminal <0>, that is, the output data WA7-0 of the word counter 43 is outputted from the multiplexer 42 as data RWA7-0 and supplied to the dual port RAM 11. Next, the CPU 2 writes the lower two bits of the address at which data is to be written in the RAM 11a to the byte counter 44, and then writes the upper eight bits to the word counter 43. As a result, the same address is set to address terminal AT1 of dual port RAM11.
supplied to Next, the CPU 2 writes "0" to the pointer counter 19 (the first process),
Next, write data is output (second process). This data is temporarily stored in the register 24 (Fig. 2).
Then, it is written into the corresponding address of the RAM 11a by the strobe signal S|MW. (iv) RAM continuous write operation When writing data continuously into the dual port RAM 11, the CPU 2 first sets the 0th, 1st, and 5th bits of the mode register 25 to “0”.
Write. This allows the signal FIX−BA,AUT
-INC and DIR-RD become "0". Signal FIX−
When BA becomes “0”, inverter 66 (third
(Figure) becomes “1” and the byte counter 44
is enabled, and OR gate 45 is enabled.
is in a through state. As a result, the two counters 44 and 43 are configured into one 10-bit up counter. Further, when the signal DIR-RD becomes "0", the data at the input terminal <0> of the multiplexer 42 (FIG. 3) is output from the multiplexer 42. Next, the CPU 2 writes the lower two bits of the start address to the byte counter 44, and
Then, the upper 8 bits are written into the word counter 43. For example, when writing data to the entire area (1024 bytes) of the RAM 11a (this case will be explained below), data "0" is written to each of the counters 44 and 43. Next, the CPU 2 writes "0" to the pointer counter 19, and then writes "0" to the pointer counter 19, and then
The data to be written to address 0 of 11a is output. This data is temporarily stored in the register 24 (Fig. 1).
Then, it is written to address 0 of the RAM 11a by the strobe signal S|MW.
In addition, the strobe signal S | MW is the OR gate 67
(FIG. 3) and is supplied to each up terminal UP of registers 44 and 43. As a result, a 10-bit counter constituted by counters 44 and 43 is incremented. Below, CPU2 is
The data to be written to the first address, second address, etc. of the RAM 11a is sequentially outputted by the above-described second process. As a result, data is sequentially written into each address of the RAM 11a, and the above-mentioned 10-bit counter is sequentially incremented. (3-2) Operation when reading by CPU2 CPU2 has registers and dual ports.
Data in the RAM 11 can be read out at any time regardless of image display. At the time of reading, a strobe signal S|MR... is output from the read decoder 21 (FIG. 2). Furthermore, data numbers are assigned in advance to readable data. The relationship among this data number, strobe signal, and read data is as follows. 0 S|MR...Data 1 in dual port RAM 11 S|ST...Status data 2 S|RR...Border register 52r (Figure 4)
Data 3 in S｜RG……Border register 52g (Figure 4)
Data 4 in S|RB...Border register 52b (Figure 4)
Here, the status data refers to the signal DTMG
(lower part of Figure 2), PG-GEL (left part of Figure 3),
This is data indicating each state of BLANK3 (lower part of Figure 4), and these signals are buffer 22 (Figure 2).
is applied to the input terminal of Next, the operation at the time of reading will be explained. (i) Data individual read operation This operation is for reading any one of the data numbers "1" to "4". In this case, the CPU 2 first writes the data number into the pointer counter 19 by the first process described above. Next, after outputting the port address PA1 to the address bus, a read pulse is output (hereinafter referred to as the third process). port address PA
When 1 is output, interface 7 outputs the signal
When the AO outputs “1” and the read pulse is output, the interface 7 outputs the signal.
It outputs "0" as WR and also outputs a pulse signal CS at the same timing as the read pulse.
When the signal AO becomes "1" and the signal WR becomes "0", the AND gate 69 shown in FIG. 2 becomes open, and the pulse signal CS is outputted through the AND gate 69. This causes the buffer 27 to enter the through state. Further, the pulse signal that has passed through the AND gate 69 is outputted as a read strobe RDST via the synchronization DFF 18 and applied to the read decoder 21 . As a result, a strobe signal corresponding to the data number in the pointer counter 19 is output from the read decoder 21. For example, when the strobe signal S|ST is output, the buffer 22 becomes a through state, and the status data is passed through the buffers 22 and 21 to the CPU.
It is output to the second data bus. Further, for example, when the strobe signal S|RR is output, the buffer 53r in FIG. 4 becomes a through state, and the register 5
The data (R color data) in 2r is output to the data bus of the CPU 2 via the buffer 53r and the buffer 27. The data output to the data bus of the CPU 2 is read into the CPU 2 at a predetermined timing. (ii) Continuous data read operation In this operation, CPU2 reads data number “1”
This is an operation when a plurality of data out of "4" data are read out consecutively. This operation is almost the same as the register continuous write operation described above, so a detailed explanation will be omitted. in this case,
The CPU 2 first writes "1" to the first bit of the mode register 25, then writes the first data number to the pointer counter 19, and thereafter repeats the third process described above. As a result, each piece of data is sequentially output to the data bus of the CPU 2. (iii) RAM data individual read operation When reading one of the data in the dual port RAM 11, the CPU 2 first writes “0” to the fifth bit of the mode register 25, and then reads the word counter 43. , writes the address of the RAM 11a into the byte counter 44 (FIG. 3). Next, data number "0" is written in the pointer counter 19, and then the third process is performed. With this third process, the read decoder 2
The strobe signal S|MR is output from 1 (Fig. 2), and the lead terminal RT of the dual port RAM 11
supplied to As a result, registers 43 and 44
Data within the address indicated by the output is read out and output from the output terminal Q1, and this output data is sent to the data bus of the CPU 2 via the buffer 27. (iv) RAM data continuous read operation In this case, the CPU 2 first writes “0” to the 0th, 1st, and 5th bits of the mode register 25, as in the case of the “RAM continuous write operation” described above. Next, the lower two bits of the start address are written into the byte counter 44, and the upper eight bits are written into the word counter 43. Next, write the data number "0" to the pointer counter 19, and from then on,
Repeat the third process. By repeating this third process, the strobe signal S|MR is repeatedly output, and a 10-bit counter consisting of registers 43 and 44 is successively incremented by this strobe signal S|MR. As a result, the data in the dual port RAM 11 is sequentially read out in byte units and output to the data bus of the CPU 2 via the buffer 27. (v) RAM data selection read operation This operation is performed by selecting the R in the RAM 11a shown in FIG.
Color data only or G color data only,
Alternatively, this operation is performed when only B color data or only attribute bits are read out continuously. In this case, the CPU 2 first sets the 0th, 1st, and 5th bits of the mode register 25 to "1" and
Write “1” and “0”. This allows the signal FIX
-BA, AUT-INC become "1" and signal DIF-RD becomes "0". When the signal FIX-BA becomes “1”,
The output of the inverter 66 (FIG. 3) becomes a "0" signal, and this "0" signal is supplied to the enable terminal EN of the byte counter 44. As a result, even if a pulse signal is thereafter supplied to the up terminal of the byte counter 44, the up-counting of the byte counter 44 is not performed, and the output of the byte counter 44 is maintained at a constant value. Also, when the signal FIX-BA becomes a “0” signal, the OR gate 45 (Fig. 3)
The output becomes a "1" signal, and this "1" signal is output to the enable terminal EN of the word counter 43. As a result, the word counter 43 thereafter operates independently as an 8-bit counter, and uses the pulse signal supplied to its up terminal UP as an up count. Furthermore, when the signal AUT-INC becomes "1", the AND gate 63 (Fig. 2) becomes open, and when the signal DIR-RD becomes "0", the output of the word counter 43 is transferred to the multiplexer 42 (Fig. 3). ) is output. Next, the CPU 2 writes a numerical value corresponding to the type of data to be read into the byte counter 44. In other words, when reading R color data, set "0", and when reading G color data, set "1".
, "2" to read B color data,
When reading the attribute bits, write "3" to each (see FIG. 5). Next, the CPU 2 writes the start address into the word counter 43 and then writes "0" into the pointer counter 19. Thereafter, the third process described above is repeated. By repeating this third process, the word counter 43 is sequentially incremented, and the output of the byte counter 44 (address data BA1-0)
Only the data determined by is sequentially read from the RAM 11a. (vi) RAM read operation based on external address data When “1” is written to the 5th bit of the mode register 25, the signal DIR-RD becomes a “11” signal,
Data at the input terminal <1> of the multiplexer 42 is output from the multiplexer 42. Therefore, in this case, terminal T7 (Fig. 1, Fig. 3)
When address data is supplied to the synchronization register 41 and multiplexer 42
The data is supplied to the dual port RAM 11 via the dual port RAM 11. In other words, it becomes possible to read data based on external address data. (3-3) Basic display operation The most basic operation of the display controller 1 is as follows.
Dot data output from VDP4 (Figure 1)
Convert DD7-0 to R, G, B color data,
Next, these color data are converted into analog color signals RS, GS, BS and output to the CRT display device 8. The operation in this case will be explained below. In this case, CPU2 first registers mode register 2.
Write “1” to the second bit of 5. As a result, the signal DISP-ENB becomes a "1" signal, and the AND gate 71 (FIG. 2) becomes open. Next, 4-bit data "0" is written into the page mask register 34 (FIG. 3). As a result, a "0" signal is supplied to each control terminal C of the multiplexers 36-39, and the output of the synchronization register 33 is outputted through the multiplexers 36-39. That is, in this case, the dot data DD7-0 is transferred to the dot data DD7-0 via the synchronization registers 33 and 35.
The signal is applied to the address terminal AT2 of the dual port RAM 11 as DDa7-0. Next, R, G, and B color data are written in the dual port RAM 11, and "0...0" (8 bits) is written as each attribute bit.
Next, border registers 50r, 50g, 50b
(Fig. 4), color data specifying the color of each border area is written. Next, the CPU 2 writes dot data (color code) into the VRAM 5 via the VDP 4, and outputs a start command to the VDP 4. VDP4 receives this start command, reads the dot data from VRAM5, and stores the read dot data as dot data DD.
7-0 and is sequentially output to the terminal T2 of the display controller 1. Also, this dot data DD7-0
In parallel with the output of , a synchronizing signal SYN.I, a blanking signal BLANK, a display timing signal DTMG, and a dot clock DCLK are output to terminals T3, T4, T5, and T17 of the display controller 1, respectively. The dot data DD7-0 supplied to the terminal T2 of the display controller 1 is sent to the registers 33 and 35.
(Fig. 3) and multiplexers 36 to 39 (upper 4 bits), the dot data DDa7-
It is applied as 0 to the address terminal AT2 of the dual port RAM 11. As a result, from the output terminals Q2 to Q4 of the dual port RAM 11,
R, G, B corresponding to dot data DDa7-0
Color data RD7-0, GD7-0, BD7-0
and attribute data AD7, AD6 (both "0") are output. And color data
RD7-0 is register 4 for one timing delay.
It is applied to one input terminal of the adder circuit 49r via the adder circuit 7r. At this time, the attribute signal AS "0" is applied to the control terminal C of the multiplexer 48r.
Data "0" of its input terminal <0> is output from r. As a result, the output of the adder circuit 49r becomes the same color data as the output of the register 49r, and this color data is transferred to the multiplexer 51.
It is supplied to the input terminal <1> of r. This multiplexer 51r outputs the color data for image display output from the adder circuit 49r during the image display period, and outputs the color data for the border color in the border register 50r during other periods. be. That is,
The display timing signal DTMG (signal indicating the image display period) output from VDP4 is DFF
72 (lower part of Figure 2)
It is synchronized with DCLK, delayed by one timing by DFF 73, and supplied to control terminal C of multiplexer 51r via AND gate 71.
As a result, during the image display period, the addition circuit 4
During the other periods, the color data in the register 50r is outputted from the multiplexer 51r and supplied to the register 52r. The register 52r converts the color data output from the multiplexer 51r into 1
The timing is delayed and the signal is supplied to the gate circuit 54r. The gate circuit 54r is a circuit whose opening/closing is controlled by the signal BLANK3. Here, the signal
BLANK3 is VDP as shown in the lower part of Figure 4.
This signal is obtained by synchronizing the blanking signal BLANK (signal indicating the screen display period) outputted from 4 with the dot clock DCLK by the synchronization register 75 and delaying it by 2 timings by the delay registers 46 and 76. Then, the gate circuit 54r
is open during the screen display period, and register 5
The color data within 2r is output to the DAC55r.
In terms of timing, the dot data DD7-0 is synchronized by the registers 33 and 35 in FIG. 3, is delayed by two timings by the registers 47r and 52r in FIG. 4, and is sent to the gate circuit 54r. applied. Therefore, dot data DD7-
0 is converted into color data and sent to the gate circuit 54r.
The timing and blanking signal applied to
This is the same timing as when BLANK is output as signal BLANK3. The color data that has passed through the gate circuit 54r is converted into an analog color signal by the DAC 55r, and output to the CRT display device 8 as a color signal RS via the amplifier 56r. The above is how color data RD7-0 is a color signal.
This is the process of being converted to RS. Color data GD7
-0 and BD-0 are also converted into color signals GS and BS through the same process. On the other hand, the synchronization signal SYN・
I is synchronized by register 75 (lower part of FIG. 4), delayed by two timings by registers 46 and 76, and outputted as a synchronizing signal via amplifier 78.
It is output to the CRT display device 8 as SYN・O.
Then, the CRT display device 8
Image display is performed in . (3-4) Blink display operation This operation is for blinking the displayed image based on the basic display operation described above. In this case, the CPU 2 writes the first and second data (4 bits each) to the page registers 30 and 31 (FIG. 3), respectively, and then writes "1" to the fourth bit of the mode register 25. , then data "1, 1," is stored in the page mask register 34.
1, 1” is written. The fourth
When “1” is written to the bit, the signal PG-
ENB becomes a "1" signal, and this "1" signal is supplied to the first input terminal of the AND gate 75 (left side in FIG. 3). The signal PG-SEL output from VDP4 (a signal that is "1" for 0.5 seconds and "0" for 0.5 seconds) is input to the second input terminal of this AND gate 75.
76. Therefore, the signal
When PG-ENB becomes a “1” signal, a signal of “1” for 0.5 seconds and “0” for 0.5 seconds is output from the AND gate 75 to the control terminal C of the multiplexer 32. As a result, the multiplexer 32 outputs a signal in the page register 30. The first data in the page register 31 and the second data in the page register 31 are output alternately every 0.5 seconds.
Then, the output data is sent to the multiplexer 36
~39 input terminal <1>. Next, when "1, 1, 1, 1" is written in the page mask register 34, a "1" signal is supplied to each control terminal C of the multiplexers 36 to 39.
Instead of the upper 4 bits of dot data DD7-0, the first and second data in page registers 30 and 31 are alternately output from multiplexers 36 to 39, and together with the lower 4 bits of dot data DD7-0, the first and second data in page registers 30 and 31 are output as dots. The data is outputted to the address terminal AT2 of the dual port RAM 11 as data DDa7-0. In other words, dot data DDa7-0 is
It will change every 0.5 seconds, so
The displayed image blinks. Furthermore, if, for example, "1, 1, 0, 0" is written in the page mask register 34, only the upper 2 bits of the dot data DD7a-0 can be changed to the data in the page registers 30 and 31. Further, for example, if "1, 0, 0, 0" is written in the page mask register 34, only the most significant bit of the dot data DDa7-0 can be changed. That is, by changing the data in the page mask register 34, it is possible to variously change the display color during blinking. (3-5) Color data modification operation This display controller 1 has dual ports.
By writing “1” to the 7th bit of the attribute bit of RAM11, the VRAM
Color data RP7 without rewriting 4.
-0, GD7-0, and BD7-0 can be changed. The operation in this case will be explained below. For example, suppose that "1" is written to the seventh bit of the attribute bit corresponding to a certain color code K1. In this case, dot data DDa
7-0, when the color code K1 is applied to the address terminal AT2 of the dual port RAM 11, the color data RD7-0, GD7 corresponding to the color code K1 is sent from the dual port RAM 11.
-0 and BD7-0 are respectively output, and "1" is output as attribute data AD7. Then, by the next dot clock DCLK, these color data are transferred to registers 47r and 47r.
At the same time, the attribute data AD7 "1" is read into the register 46, and thereby the attribute signal AS becomes a "1" signal. When the attribute signal AS becomes a "1" signal and this "1" signal is applied to the control terminal C of the multiplexer 48r, the color data in the register 52r is transferred to the multiplexer 48.
The color data is supplied to the adder circuit 49r via r, and the adder circuit 49r outputs new color data obtained by adding the color data in the register 47r and the color data in the register 52r. Here, the color data in register 52r is data that determines the color of a dot to be displayed one dot clock DCLK before the color data in register 47r. Therefore, adding the color data in register 52r to the color data in register 49r means adding the color data of a dot displayed one dot clock DCLK ago to the color data in register 47r. do. The above is the modification operation for color data RD7-0. Color data GD7-0, BD7-
Also for 0, the attribute signal AS is “1”
A similar modification is made in the case of "Effects of the Invention" As explained above, according to the present invention, there are first and second registers into which color change data for changing color data is written, and color change data written in the first and second registers. a first selection means for alternately outputting color change data at predetermined timing; and a bit specification for specifying which bit of the output of the first selection means is to be replaced with a corresponding bit of the color data. replacing the plurality of bits specified by the bit designation data among the color change data output by the third register for outputting data and the first selection means with the corresponding bits of the color code;
Since the second selection means outputs as a new color code and the conversion means converts the new color code outputted by the second selection means into the color data, By changing the data, the display color during blinking can be changed in various ways.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a color display device using a display controller 1 according to an embodiment of the present invention, FIGS. 2 to 4 are circuit diagrams showing details of the display controller 1, and FIG. The figure shows the configuration of the control section, FIG. 3 shows the configuration of the RAM address forming section, and FIG. 4 shows the dual port RAM 11 and color data conversion circuit 12.
FIG.
It is a figure showing the composition of RAM11a. 1...Display controller, 11...Dual port
RAM, 12r, 12g, 12b...Color data conversion circuit, 30, 31...Page register, 32,
36 to 39...Multiplexer, 34...Page mask register.

Claims (1)

[Claims] 1. A color code that corresponds one-to-one to the display color,
In a display controller that converts the color data into color data, further converts these color data into analog color signals, and outputs the analog color signals, the display controller includes: (a) first and second registers into which color change data for changing the color data is written; b) a first selection means that alternately outputs the color change data written in the first and second registers at a predetermined timing; and (c) an output of the first selection means. a third register that outputs bit designation data specifying whether to replace the bits of the color data with the corresponding bits of the color data; (d) of the color change data output by the first selection means, the bit designation data; (e) a second selection means for replacing a plurality of bits specified by the color code with corresponding bits of the color code and outputting the resultant color code as a new color code; A display controller comprising: conversion means for converting a color code into the color data.