JPH04291634A - Fault detecting circuit for microcomputer - Google Patents

Abstract

PURPOSE:To easily detect a fault in a microcomputer (MC) by providing this fault detecting circuit with a detection circuit for detecting the output of the prescribed number of reset pulses or more from a reset ID having a watch-dog function. CONSTITUTION:When the MC 1 runs away, i.e., the reset IC 2 having the watch- dog function can not obtain a pulse signal from the MC 1 within a fixed interval, a reset pulse is outputted from the IC 2 to the MC 1, which is reset by the reset pulse and returned to a normal state. At the time of generating a fault in which the MC 1 can not be normally restored only by the reset pulse, reset pulses are continuously outputted at a prescribed time interval until a pulse signal is inputted. Thereby when the number of reset pulses exceeds a prescribed value, the detection circuit 3 outputs an output signal to inform the generation of a failure in the MC 1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure detection circuit for a microcomputer applied to a pump controller or the like.

0002

2. Description of the Related Art There is a microcomputer that is equipped with a reset IC with a watchdog function to reset the microcomputer in the event of a runaway.

0003

[Problem to be solved by the invention] However, simply adding a reset IC with a watchdog function to a microcontroller will not solve the problem.
Although this method is effective in preventing a runaway microcomputer, it is no longer effective in cases where the microcomputer breaks down for some reason and the microcomputer cannot return to normal with just a reset pulse.

[0004] In this case, it is necessary to promptly inform the outside that the control has become uncontrollable and take measures such as switching from automatic to manual. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a microcomputer failure detection circuit capable of detecting a failure of the microcomputer in a system using a microcomputer and a reset IC with a watchdog function.

[0005]

[Means for Solving the Problems] The microcomputer failure detection circuit of the present invention includes a microcomputer that outputs pulse signals at regular intervals during normal operation, and a microcomputer that receives the pulse signals of the microcomputer within a predetermined period of time equal to or longer than the fixed interval. a reset IC with a watchdog function that outputs a reset pulse to the microcomputer to reset the microcomputer when the pulse signal is not input to the microcomputer; and the reset IC with the watchdog function.
and a detection circuit that receives the reset pulses and outputs an output signal when the number of reset pulses exceeds a predetermined value.

[0006]

[Operation] According to the structure of the present invention, when the microcomputer goes out of control, that is, when the reset IC with watchdog function cannot obtain a pulse signal from the microcomputer within a certain interval, the reset IC with watchdog function sends a reset pulse to the microcomputer. This will reset the microcontroller and return it to normal. In the event of a failure in the microcontroller that cannot be restored to normal with a reset pulse alone, reset pulses are output continuously at predetermined time intervals until a pulse signal is input, so the detection circuit detects when the number of reset pulses exceeds a predetermined value. When this happens, an output signal is output, and from this output signal it can be easily determined that the microcomputer is malfunctioning. Therefore, it is effective for systems that require countermeasures such as switching from automatic to manual when the microcomputer becomes uncontrollable.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be explained with reference to FIGS. 1 and 2. In other words, the failure detection circuit of this microcomputer consists of microcomputer 1 and a reset IC with watchdog function.
2 and a detection circuit 3. The microcomputer 1 is a well-known one used, for example, in a pump controller, and has an output terminal 14 that outputs a pulse signal at regular intervals during normal operation, and a reset terminal 15.

[0008] The reset IC 2 with watchdog function is
It inputs the pulse signal of the microcomputer 1 and outputs a reset pulse to the microcomputer 1 to reset the microcomputer 1 when the pulse signal is not input within a predetermined period of time equal to or more than the predetermined interval, and is a well-known device. Details are omitted. 16 is a clock terminal for inputting a pulse signal, and 17 is a reset pulse output terminal.

The detection circuit 3 receives the reset pulses from the watchdog function reset IC 2 and outputs an output signal when the number of reset pulses exceeds a predetermined value. In the embodiment, when a charging capacitor is charged with a reset pulse and the charging voltage reaches a predetermined level or higher corresponding to a predetermined value of the number of reset pulses, an output signal can be output.

That is, this detection circuit 3 is connected to the reset pulse output terminal 1 of the reset IC 2 with watchdog function.
7 is connected to a charging capacitor 7 via an inverter 4 having hysteresis characteristics and an inverting function, a diode 5, and a resistor 6, and the connection point of the charging capacitor 7 with the resistor 6 is connected to the non-inverting operational amplifier 9 via a resistor 8. Connected to the input terminal. 10 is a discharge resistance. A connection point between a voltage setting resistor 12 and a voltage dividing resistor 11 is connected to an inverting input terminal of the operational amplifier 9, and a DC power source E is connected to the voltage dividing resistor 11. On the other hand, a relay 13 and a drive transistor 18 are connected in series to a DC power source E, and a series circuit of a resistor 20 and a thyristor 19 is connected in parallel thereto. And a resistor 21 and a capacitor 2 are connected to the output terminal of the operational amplifier 9.
3 are connected in series, and the connection point of the capacitor 23 and the resistor 21 is connected to the trigger terminal of the thyristor 19. 2
2 is a discharge resistor, 24 and 25 are resistors on the base side of the transistor 18, 26 is a capacitor thereof, and 27 is a surge absorption diode of the relay 13.

Further, circuits A and B are for suppressing the unstable operation of the circuit when the DC power supply E is turned on.
has a diode 28, an operational amplifier 29, and an electrolytic capacitor 30, so that the operational amplifier 29 becomes high by charging the electrolytic capacitor 30 after the reset IC 2 with watchdog function is ready to output a reset pulse. I have to. Circuit B is relay 3
7. It has a driving transistor 38 and an electrolytic capacitor 39, and the electrolytic capacitor 39 is connected later than the time when the relay 13 is operated by the DC power source E and the normally closed contact 46 is turned off.
is charged, the drive transistor 38 is turned on, the relay 37 is operated, and the normally open contact 47 is turned on. 40 to 42 are resistors, 43 is a capacitor, and 44 is a surge absorption diode.

[0012]The output circuit 45 includes relays 13 and 37.
A normally closed contact 46 and a normally open contact 47 are connected in series, and an alarm circuit (not shown) that displays or sounds is connected to this, and when both the normally closed contact 46 and the normally open contact 47 are on, the output circuit 45 can output an output signal and operate the alarm circuit. While referring to the time chart in Figure 2,
The operation will be explained. Note that the positions on the circuit corresponding to each time chart are shown in FIG. The DC power supply E outputs the voltage shown in FIG. When the DC power supply E is turned on, the reset I with watchdog function is activated as shown in the same figure (c).
The pariset pulse output terminal 17 of C2 becomes in an operating state in which it can output a reset pulse, and the output terminal of the inverter 4 becomes in its inverted state as shown in FIG. 4(d). Also in the same figure (g
), when the thyristor 19 is off, the drive transistor 18 is on, the relay 13 operates, and the normally closed contact 4 is turned on.
6 is off.

Furthermore, as shown in FIG. 2(e), after the watchdog function reset IC 2 enters the operating state shown in FIG. 2(c), the operational amplifier 29 of circuit A becomes high. Therefore, the charging capacitor 7 is not charged by then and the operational amplifier 9 is low. Similarly, in circuit B, normally closed contact 46
After turning off as shown in (g) in the same figure, the relay 37 operates and the normally open contact 47 turns on as shown in (h) in the same figure. Therefore, the normally closed contact 46 and the normally open contact 47 are not turned on at the same time until then.

After the power is turned on, the microcomputer 1 outputs pulse signals at regular intervals (the first three pulses are shown) during normal operation as shown in FIG. is being entered. Here, if the microcomputer 1 goes out of control at time t1 shown in FIG. If no pulse signal is input,
A reset IC with watchdog function as shown in the same figure (c)
2 outputs a reset pulse P, which resets the microcomputer 1 and returns to normal. As a result, the microcomputer 1 again outputs a pulse signal as shown in FIG. 2(b) (four pulses are shown).

Next, when the microcomputer 1 fails at time t3, the pulse signal stops for a predetermined time t2 or more, so the reset IC 2 with watchdog function outputs a reset pulse P, but the microcomputer 1 does not return to normal. If a pulse signal is not input within a predetermined time t2 after outputting the reset pulse, the reset pulse P is output again, and from then on, the reset pulse P is periodically and continuously repeated until a pulse signal is input from the microcomputer 1. (5 are shown).

At this time, the output of the inverter 4 of the detection circuit 3 is the inverted version of the reset pulse P, as shown in FIG. 3(d). The charging capacitor 7 is then charged by the reset pulse P as shown in FIG. 2(f). That is, at the time t1 when the microcomputer 1 runs out of control, there is only one reset signal, so the charging voltage is less than the voltage e of the setting resistor 12, but due to a failure in the microcomputer 1, it is not reset by the reset pulse P, and the reset pulse shown in FIG. When the number exceeds three, the charging voltage of the charging capacitor 7 becomes equal to or higher than the level of the voltage e. At this time, the output terminal of the operational amplifier 9 becomes high, which is input to the trigger terminal of the thyristor 19 and turns on the thyristor 19. Therefore, the drive transistor 18 is turned off, and the relay 13 is turned off, as shown in FIG. The normally closed contact 46 is turned on. Therefore, the series circuit of the normally open contact 47 and the normally closed contact 46 of the output circuit 45 becomes closed as shown in FIG. 4(i), and an output signal can be output to the alarm circuit.
An alarm signal can be generated.

According to this embodiment, when the microcomputer 1 goes out of control, that is, when the reset IC 2 with a watchdog function cannot obtain a pulse signal from the microcomputer 1 within a fixed interval, the reset IC 2 with a watchdog function issues a reset pulse to the microcomputer. is output, which causes microcontroller 1 to
will be reset and return to normal. When the microcomputer 1 fails to return to normal with a reset pulse alone, reset pulses are continuously output at predetermined time intervals until a pulse signal is input, so the detection circuit 3 detects when the number of reset pulses exceeds a predetermined value. When this occurs, an output signal is output, and from this output signal it can be easily known that the microcomputer 1 is malfunctioning.

[0018]

[Effects of the Invention] The microcomputer failure detection circuit of this invention has the following features:
In a system using a microcontroller and a reset IC with a watchdog function, a detection circuit is installed to detect when a predetermined number of reset pulses are output from the reset IC with a watchdog function due to the microcontroller not being reset. Failures can be easily detected. Therefore, it is effective for systems that require countermeasures such as switching from automatic to manual when the microcomputer becomes uncontrollable.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a time chart thereof.

[Explanation of symbols]

1 Microcomputer 2 Reset IC with watchdog function 3
detection circuit

Claims (1)

[Claims] 1. A microcomputer that outputs a pulse signal at regular intervals during normal operation, and a microcomputer that receives the pulse signal from the microcomputer and resets the microcomputer when the pulse signal is not input within a predetermined time period that is longer than the regular interval. a reset IC with a watchdog function that outputs a reset pulse to the microcomputer, and a reset IC with a watchdog function that outputs a reset pulse to the microcomputer;
A failure detection circuit for a microcomputer, comprising: a detection circuit that inputs the reset pulse of C and outputs an output signal when the number of reset pulses exceeds a predetermined value.