JPH04291732A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To accelerate miniaturization of a field effect transistor by forming conductive films for first and second gates by one etching, and forming T-shaped sectional gates. CONSTITUTION:An n-type channel layer 2 is formed on a main surface of a substrate 1. Then, after conductive films for first and second gates are sequentially laminated on the entire surface of the substrate 1, a photoresist mask 7 is formed on a region to be formed with the gates. In this case, the film for the second gate is formed of a material having a lower etching rate than that of the film for the first gate of a lower layer. Then, the films for the first and second gates are patterned by one dry etching. In this case, since the film for the first gate having higher etching gate than that of the film for the second gate is sidewisely etched larger at a lower sidewall of the mask 7, a T-shaped sectional gate 8 is obtained.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a field effect transistor (Field Effect Transistor).
Regarding the manufacturing technology of FET (hereinafter referred to as FET), in particular
The present invention relates to a technology that is effective when applied to miniaturization.

0002

[Prior Art] As the miniaturization of FETs progresses and the gate length becomes shorter, the threshold voltage (VTH) increases.
Deterioration of the electrical characteristics of FETs due to short channel effects, such as fluctuations in FETs, becomes a serious problem.

One of the measures to suppress the short channel effect of FET is the technique described in Japanese Patent Laid-Open No. 115268/1983. In this conventional technology, the FET gate is processed so that its cross section is T-shaped, and when impurity ions are implanted into the substrate to form the source and drain, the T-shaped gate is masked and ions are ionized in a self-aligned manner. The implantation is intended to suppress the short channel effect of the FET.

In the above conventional technology, in order to form a T-shaped gate, first the first conductive film for gate is processed by etching to form a gate with a short gate length, and then,
A method is used in which a second gate conductive film deposited on the gate is processed by etching to form a gate with a long gate length.

[0005]

[Problems to be Solved by the Invention] In the prior art, each of the first and second conductive films for gates is processed by etching using a photoresist as a mask.
There is a problem in that it is impossible to form a T-shaped gate having a finer gate length than the alignment precision of the photoresist mask used when forming the photoresist pattern.

Furthermore, even if the gate length exceeds the mask alignment accuracy, a T-shaped gate with left and right asymmetrical properties is formed due to misalignment of the photoresist. If the source and drain are formed in the same direction, there is a problem that the source and drain become asymmetrical and the electrical characteristics of the FET deteriorate.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technique that can promote miniaturization of FETs.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0009]

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows.
It is as follows.

In the method for manufacturing a field effect transistor according to the present invention, a second conductive film for gates having a lower etching rate is deposited on the first conductive film for gates deposited on the substrate, and A gate having a T-shaped cross section is formed by processing the first and second conductive films for gates in a single etching process.

[0011]

[Operation] According to the above-described means, by processing the first and second conductive films for gates in one etching,
Since misalignment of the photoresist mask does not occur between the first conductive film for gate and the second conductive film for gate, the T A glyph-shaped gate can be formed.

Furthermore, by etching the first and second conductive films for gates in a single process, it is possible to form a symmetrical T.
Since a T-shaped gate can be formed, this T-shaped gate can be used as an ion implantation mask to self-align the source,
When a drain is formed, the source and drain will not become asymmetrical.

[0013]

EXAMPLE A method of manufacturing a MESFET according to this example will be described below with reference to FIGS. 1 to 7.

First, an n-type channel layer 2 is formed on the main surface of a semi-insulating semiconductor substrate 1 made of GaAs (gallium arsenide). To form the n-type channel layer 2, first, as shown in FIG.
As shown in FIG.
Next, as shown in FIG. The impurities are activated by heat-treating the substrate 1 in a hydrogen gas atmosphere at about 800°C.

Next, as shown in FIG. 3, a first gate conductive film 5 and a second gate conductive film 6 are formed on the entire surface of the substrate 1.
After sequentially depositing the photoresist mask 7, a photoresist mask 7 is formed on the region where the gate is to be formed. In this case, the second gate conductive film 6 is provided with a material having a lower etching rate than the underlying first gate conductive film 5. Furthermore, in this embodiment, the second gate conductive film 6 is
It is made of a material that has a lower electrical resistance than the first conductive film 5 for gate below.

A possible combination of conductive film materials that satisfies the above two conditions is, for example, a combination of W (tungsten) and its silicide (WSix). In this case, since W has a lower etching rate than WSix and a lower electrical resistance than WSix,
W is used as the second conductive film 6 for gate, and W is used for the first conductive film 5 for gate underneath. W is deposited on the substrate 1 by a sputtering method, and WSix is deposited by a sputtering method or a CVD method.

Next, the first gate conductive film 5 and the second gate conductive film 6 are patterned by one dry etching. At this time, the first conductive film 5 for gate, which has a higher etching rate than the second conductive film 6 for gate,
Since the side wall under the photoresist mask 7 is side-etched to a larger extent, a gate 8 having a T-shaped cross section is obtained as shown in FIG.

Next, after removing the photoresist mask 7 by etching, a new photoresist mask 9 is formed around the active region on the main surface of the substrate 1, as shown in FIG. and the above gate 8
An n-type impurity such as Si is ion-implanted into the substrate 1 using a mask.

Next, after removing the photoresist mask 9 by etching, the substrate 1 is heat-treated in, for example, arsine to activate the Si, thereby forming the source and drain of the MESFET, as shown in FIG. A pair of n+ type semiconductor regions 10 and 11 are formed on both sides of gate 8 in a self-aligned manner.

Thereafter, as shown in FIG.
By forming ohmic electrodes 12 on each of the + type semiconductor regions 10 and 11, a MESFET is completed.

According to the MESFET manufacturing method comprising the above steps, the following actions and effects can be obtained.

(1). The first gate conductive film 5 and the second gate conductive film 6 are processed by one etching process to form a T.
Since the gate 8 is formed in the shape of a letter, misalignment of the photoresist mask does not occur between the first conductive film 5 for gate and the second conductive film 6 for gate. Thereby, a T-shaped gate having a fine gate length can be formed regardless of the alignment accuracy of the photoresist mask.

(2). The first gate conductive film 5 and the second gate conductive film 6 are processed by one etching process to form a T.
Since the gate 8 is formed in the shape of a letter, the shape of the gate 8 does not become asymmetric between the left and right sides. As a result, when the source and drain are formed in a self-aligned manner using this T-shaped gate 8 as a mask for ion implantation, the source and drain will not become asymmetrical, so deterioration of the electrical characteristics of the MESFET can be prevented. .

(3). The above (1) and (2) promote miniaturization of MESFETs.

(4). Since W, which has a lower electric resistance than WSix, is laminated on top of WSix, which forms part of the T-shaped gate 8, the parasitic resistance (Rg) of the gate 8 is reduced.
The switching operation of the FET is sped up.

[0026] Above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. It goes without saying that there is.

In the above embodiment, a combination of W and WSix was exemplified as the first and second conductive films for gates, but the combination is not limited to this, and for example, Mo,
An appropriate combination of Ti, Ta, or their silicides may be used.

In the above embodiment, a semi-insulating semiconductor substrate made of GaAs is used, but the present invention is not limited to this, and a compound semiconductor substrate such as InGaAs, InAlAs, InGaAsP or the like may also be used.

In the above embodiments, the case where the method is applied to the manufacturing method of MESFET has been explained, but the present invention is not limited to this.
Semiconductor) Various FE such as FET
It can be applied to the manufacturing method of T.

[0030]

[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions will be briefly explained as follows.
It is as follows.

A second conductive film for gates having a lower etching rate is deposited on the first conductive film for gates deposited on the substrate, and the first and second conductive films for gates are combined. By forming a gate with a T-shaped cross section through multiple etching processes, it is possible to form a T-shaped gate with a finer gate length than the alignment accuracy of the photoresist mask, which facilitates the miniaturization of FETs. can be promoted.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor substrate showing a method for manufacturing a field effect transistor, which is an embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor substrate showing a method for manufacturing a field effect transistor, which is an embodiment of the present invention.

FIG. 3 is a plan view of a semiconductor substrate showing a method for manufacturing a field effect transistor, which is an embodiment of the present invention.

FIG. 4 is a plan view of a semiconductor substrate showing a method for manufacturing a field effect transistor, which is an embodiment of the present invention.

FIG. 5 is a plan view of a semiconductor substrate showing a method for manufacturing a field effect transistor according to an embodiment of the present invention.

FIG. 6 is a plan view of a semiconductor substrate showing a method for manufacturing a field effect transistor, which is an embodiment of the present invention.

FIG. 7 is a plan view of a semiconductor substrate showing a method for manufacturing a field effect transistor, which is an embodiment of the present invention.

[Explanation of symbols]

1 Semiconductor substrate 2 N-type channel layer 3 Photoresist mask 4 Cap membrane 5 First gate conductive film 6 Second gate conductive film 7 Photoresist mask 8 Gate 9 Photoresist mask 10 n+ type semiconductor region 11 n+ type semiconductor region 12 Ohmic electrode

Claims (3)

[Claims] 1. A second conductive film for gates having a lower etching rate than the first conductive film for gates is deposited on the first conductive film for gates deposited on the substrate, and A method for manufacturing a field effect transistor, comprising the step of forming a gate having a T-shaped cross section by etching a second conductive film for a gate. 2. The method for manufacturing a field effect transistor according to claim 1, wherein a conductive material having a lower electric resistance than the first conductive film for gate is used as the second conductive film for gate. 3. The field effect transistor according to claim 1, wherein when impurity ions are implanted into the substrate to form the source and drain, the ion implantation is performed in a self-aligned manner while masking the gate. manufacturing method.