JPH04292006A - Flat gain amplifier - Google Patents

Abstract

PURPOSE:To make a bias circuit unnecessary, and also, to widen a flat gain band in respect of a flat gain amplifier by a CMOS circuit. CONSTITUTION:First p- and n-channel field effect transistors 3,4 are cascade- connected between power supply 1 and the ground 2, and the gates of these transistors 3,4 are connected in common so as to be an input terminal 5. Besides, second p- and n-channel field effect transistors 6,7 are cascade-connected between the power supply 1 and the ground 2, and their cascade-connection point, the gates of these transistors 6,7, and the cascade-connection point of the first p- and n-channel field effect transistors 3,4 are connected in common so as to be an output terminal 8.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat gain amplifier using a CMOS circuit. CMOS (Complete)
mentary Metal Oxide Se
The microconductor) circuit is a combination of a p-channel field effect transistor and an n-channel field effect transistor, and has a low power consumption structure.
It is widely used as a semiconductor integrated circuit. It is desired to significantly widen the flat gain band of an amplifier using such a CMOS circuit.

0002

[Prior Art] FIG. 4 is an explanatory diagram of a conventional amplifier.
Between the power supply (VDD) 11 and the ground (G) 12,
n-channel field effect transistors 13-15, 20, 2
1 and p-channel field effect transistors 16 to 19 (hereinafter abbreviated as transistors).
6, 18, 20 are connected in cascade, and transistors 17, 1
9 and 21 are connected in cascade, transistor 20 is diode-connected, and its gate is connected to the gate of transistor 21.

Furthermore, the transistor 13 is connected to the connection point between the transistors 16 and 18, and the transistor 14 is connected to the connection point between the transistors 17 and 19.
Transistor 1 is connected between the connection point with 14 and ground 12.
Connect 5. Also, a common bias voltage VB1 is applied to the gates of transistors 16 and 17, and transistors 18 and
A common bias voltage VB2 is applied to the gate of the transistor 19, and a bias voltage VB3 is applied to the gate of the transistor 15. In addition, input terminals INP and INN are connected to the gates of transistors 13 and 14, respectively, and transistors 19 and 14 are connected to input terminals INP and INN, respectively.
The output terminal OUT is connected to the connection point 21 to form a differential amplifier.

[0004] This amplifier has a CMOS circuit configured by connecting a p-channel transistor and an n-channel transistor in series between a power supply 11 and a ground 12, and its DC (direct current) gain is 60 dB. , the flat gain band is 100kHz.

The basic configurations of amplifiers shown in FIGS. 5 and 6 are also known, and both are CMOS inverter circuits. That is, in FIG. 5, a p-channel field effect transistor 31 and an n-channel field effect transistor 32 are connected in cascade,
A bias voltage is applied from the bias power supply 33 to the gate of the p-channel field-effect transistor 31, and the input terminal 34 is connected to the gate of the n-channel field-effect transistor 32. The output terminal 35 is connected to the connection point, and when the input terminal 34 becomes high level, n
Since the channel field effect transistor 32 is turned on,
The output terminal 35 becomes low level, and on the contrary, the input terminal 34
When becomes low level, the n-channel field effect transistor 32 is turned off, so the p-channel field effect transistor 31 is turned on, and the output terminal 35 becomes high level.

In FIG. 6, a p-channel field effect transistor 36 and an n-channel field effect transistor 37 are connected in cascade, and the gates of the p-channel field effect transistor 36 and the n-channel field effect transistor 37 are commonly connected to an input terminal 38. and p-channel field effect transistor 36
An output terminal 39 is connected to a connection point between the N-channel field effect transistor 37 and the N-channel field effect transistor 37. This circuit also has the same effect as the circuit shown in FIG.
9 and is inverted and output.

FIG. 7 is an explanatory diagram of a conventional broadband amplifier, in which a p-channel field effect transistor 41 and an n-channel field effect transistor 42 are connected in cascade, and a bias power supply 4 is connected to the gate of the p-channel field effect transistor 41.
Applying a bias voltage from 3, connecting the input terminal 44 to the gate of the n-channel field effect transistor 42, and connecting the output terminal 45 to the connection point between the p-channel field effect transistor 41 and the n-channel field effect transistor 42, A diode-connected n-channel field effect transistor 46 is connected, and corresponds to a configuration in which a diode-connected n-channel field effect transistor 46 is connected to the basic configuration shown in FIG. As shown in FIG. 8, the frequency characteristic of this amplifier is a flat gain up to about 100 MHz.

[0008]

[Problems to be Solved by the Invention] Amplifiers used in devices that process high-speed signals such as optical signals are required to have a wide flat gain band corresponding to the high-speed signals. On the other hand, the conventional amplifier shown in FIG. 4 has a GB product of about 100 MHz, but a flat gain band of 1
00kHz, and the DC gain and band fluctuate due to variations in the manufacturing process, so there is a drawback that the configuration as it is cannot be used as a flat gain amplifier.Furthermore, it requires a large number of bias circuits, so it is not practical in practice. The disadvantage is that the circuit scale becomes large.

In addition, in the basic configuration of the conventional amplifier shown in FIGS. 5 and 6, due to miniaturization technology brought about by advances in semiconductor technology, the unity gain band (band where the gain is 0 dB) is now 1 GHz. Although it is possible, the flat gain band is limited to about 10 MHz. Therefore,
A configuration as shown in FIG. 7 has been proposed, and the flat gain band is approximately 100 MHz. The amplifier shown in FIG. 7 has the advantage of being less susceptible to manufacturing process variations because the gain of the amplifier is determined by the size ratio of the n-channel field effect transistors 42 and 46. but,
It is difficult to make the flat gain band wider than this. Furthermore, since a bias circuit for the p-channel field effect transistor 41 is required, there is a drawback that the actual circuit scale becomes large. The present invention aims to eliminate the need for a bias circuit and widen the flat gain band.

0010

[Means for Solving the Problems] A flat gain amplifier of the present invention has a first p-channel field effect transistor 3 and a first n-channel field effect transistor 4 connected in cascade between a power supply 1 and a ground 2. The gates of the first p-channel field effect transistor 3 and the first n-channel field effect transistor 4 are commonly connected to form an input terminal 5, and a second A p-channel field effect transistor 6 and a second n-channel field effect transistor 7 are connected in cascade, and this cascade connection point is
The gates and drains of the second p-channel field-effect transistor 6 and the second n-channel field-effect transistor 7 are commonly connected, and the first p-channel field-effect transistor 3 and the first n-channel field-effect transistor 4
The cascade connection point and the output terminal 8 are connected in common.

[0011]

[Operation] First p-channel field effect transistor 3 and first n-channel field effect transistor 4 connected in cascade.
A second diode-connected p-channel field-effect transistor 6 is connected in parallel to the first p-channel field-effect transistor 3, and a second diode-connected n-channel field-effect transistor 7 is connected in parallel to the first p-channel field-effect transistor 3. The first p-channel field-effect transistor 3 is connected in parallel to the first n-channel field-effect transistor 4;
In order to increase the slope of the drain voltage versus drain current characteristic with the first n-channel field effect transistor 4,
It lowers the DC gain and widens the flat gain band.

0012

[Embodiment] FIG. 1 is a circuit diagram of an embodiment of the present invention, in which 1 is a power supply, 2 is a ground, 3 and 6 are first and second p-channel field effect transistors, and 4 and 7 are first and second p-channel field effect transistors. 2 is an n-channel field effect transistor, 5 is an input terminal, and 8 is an output terminal. A first p- and n-channel field-effect transistor 3, 4 is connected in cascade between a power supply 1 and a ground 2, the gates of which are used as an input terminal 5;
The channel field effect transistors 6 and 7 are connected in cascade between the power source 1 and the ground 2, the cascade connection point and their gates and drains are commonly connected, and a first p
and a cascade connection point of n-channel field effect transistors 3 and 4 are commonly connected to form an output terminal 8.

The second p- and n-channel field-effect transistors 6, 7 are diode-connected and connected in parallel to the first p- and n-channel field-effect transistors 3, 4, respectively. Further, p and n channel field effect transistors are connected in cascade between the power supply 1 and the ground 2 to form a CMOS circuit. Further, by connecting the gates of the first p- and n-channel field effect transistors 3 and 4 in common to form an input terminal 5, a bias circuit is not required.

FIG. 2 is a drain current/voltage characteristic curve diagram in the circuit shown in FIG. 1, where the horizontal axis represents the drain voltage VD.
, the vertical axis indicates the drain current ID. Also, PCH is a group of characteristic curves of p-channel field effect transistor 3, and NCH is n
A group of characteristic curves of a channel field effect transistor 4,
The arrows indicate the relationship between the gate voltage VG and the curve groups PCH and NCH. Further, the intersection of the curve groups PCH and NCH becomes the operating point of the amplifier.

As mentioned above, by connecting the diode-connected second p and n channel field effect transistors 6 and 7 in parallel to the first p and n channel field effect transistors 3 and 4, the drain current and voltage can be increased. Characteristic curve group PC
Since the slope of H,NCH is relatively close to vertical,
The DC gain can be kept low and the flat gain band can be widened.

FIG. 3 is an open loop gain characteristic curve diagram of the amplifier according to the embodiment of the present invention shown in FIG.
It is a characteristic curve diagram when the drain current of the n-channel field effect transistors 3 and 4 is 0.8 mA, and the drain current of the second p- and n-channel field effect transistors 6 and 7 is 0.2 mA, and the DC gain is 10dB, flat gain band approximately 200MHz, unity gain band 1
It has exceeded GHz. That is, it is possible to eliminate the need for a bias circuit and widen the flat gain band.

[0017]

As explained above, the present invention connects first p and n channel field effect transistors 3 and 4 in cascade and connects second p and n channel field effect transistors 6 and 7 which are diode connected. connected in parallel to first p- and n-channel field effect transistors 3, 4, respectively;
The gates of the first p- and n-channel field effect transistors 3 and 4 are connected in common to form an input terminal 5, which eliminates the need for a bias circuit, and also
Drain current of channel field effect transistors 3 and 4
Since the voltage characteristic curve can be made close to vertical, DC
I was able to keep the gain low and widen the flat gain band. That is, there is an advantage that a wideband flat gain amplifier can be constructed with a simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a drain current/voltage characteristic curve diagram of an example of the present invention.

FIG. 3 is an open loop gain characteristic curve diagram of an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a conventional amplifier.

FIG. 5 is an explanatory diagram of the basic configuration of a conventional amplifier.

FIG. 6 is an explanatory diagram of the basic configuration of a conventional amplifier.

FIG. 7 is an explanatory diagram of a conventional wideband amplifier.

FIG. 8 is a frequency characteristic curve diagram of a conventional wideband amplifier.

[Explanation of symbols]

1 Power supply 2 Ground 3 First p-channel field effect transistor 4 First n-channel field effect transistor 5 Output terminal 6 Second p-channel field effect transistor 7 Second n-channel field effect transistor 8 Output terminal

Claims (1)

[Claims] Claim 1: A first p-channel field effect transistor (3) and a first n-channel field effect transistor are connected between a power supply (1) and a ground (2).
A channel field effect transistor (4) is connected in cascade,
the first p-channel field effect transistor (3) and the first p-channel field effect transistor (3);
The gates of the n-channel field effect transistors (4) are commonly connected to serve as an input terminal (5), and the second p-channel field effect transistor (6) and the second p-channel field effect transistor (6) are connected between the power supply (1) and the ground (2). 2 n-channel field effect transistors (
7) are connected in cascade, and the cascade connection point is commonly connected to the gates and drains of the second p-channel field effect transistor (6) and the second n-channel field effect transistor (7), and A flat device characterized in that a cascade connection point between the first p-channel field effect transistor (3) and the first n-channel field effect transistor (4) is commonly connected to form an output terminal (8). gain amplifier.