JPH0429233B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOS field effect transistor, in particular a MOS field effect transistor with a short channel length.

As the channel length of MOS type (generally speaking MIS type) field effect transistors is shortened to improve the degree of integration, short channel effects such as punch-through occur, as is well known. As one method for preventing this, a method has been proposed in which impurity ions are implanted into a limited region under the gate electrode to form a high impurity concentration layer 12, as shown in FIG. In this figure, 10 is a p-type silicon substrate, 12 is the above-mentioned p ⁺ channel doped region, and 24 is a mask layer for implanting impurity ions such as boron B. Ion implantation is performed as shown in Figure a to form a region 12, and then a gate oxide film 1 is formed by a normal silicon gate process or the like as shown in Figure b.
4, gate electrode 20, source, drain region, 1
6, 18 are formed. Reference numeral 22 denotes a field oxide film, which is first formed by a selective oxidation method or the like before the step shown in FIG. By the way, in step a, when ions are implanted into the silicon substrate using a mask layer such as photoresist 24 as a mask, and the photoresist 24 is removed to proceed to the next step b,
Since the ion implantation part 12 cannot be visually confirmed, if the resist 24 is removed, it becomes impossible to know where the ion implantation part 12 is located. Of course, the marks for mask alignment are marked on the periphery of the wafer, so using this as a reference will give you a rough idea, but it will not be possible to make fine adjustments for accurate alignment.

The present invention improves these points and proposes a MOS transistor structure that can provide a high-quality channel configuration. That is, in the present invention, as shown in FIG. 2, the surface portion of the p type silicon substrate where the p ⁺ type channel doped region 12 is located is etched and recessed.
That is, a photoresist 24 is applied to the surface of the substrate 10, patterned to form a window W in the area where the region 12 is to be formed, and silicon is etched using the patterned resist 24 as a mask.
Make a depression H with a depth of about [Å]. Next, impurities such as boron B are ion-implanted again using the resist 24 as a mask to form the p ⁺ type channel doped region 1.
Make 2. Thereafter, the gate oxide film 14, source and drain regions 1 are formed by normal steps as shown in FIG.
6, 18, make the gate electrode 20. In this way, since there is a recess H, mask alignment during patterning of the gate electrode etc. becomes easy, and the gate electrode 20 and gate oxide film 14 can be formed correctly at a predetermined position in the middle of the field oxide film 22, in this example, at the center. I can do it. Further, when forming the channel doped region 12, deep ion implantation is performed, but in this case, of course, the photoresist film 24 must be made thicker, otherwise the impurity ions will penetrate and the resist film will become useless. However, thick resist film 2
No. 4 is difficult to perform fine or highly accurate patterning. If this point is etched to create a depression H and ion implantation is performed in such a state, the ion implantation depth can be reduced by the depth of the depression H, so the resist film 24 can be thin, fine, and dense. It becomes possible to form elements. In addition, there is a possibility that surface defects or contamination may occur on the substrate surface due to the process of forming the field oxide film 22, etc., but if the surface is etched and removed to form the depression H, these surface defects and contamination will be removed at the same time. be done. Note that the channel consists of the surface portion of region 12 and the substrate surface portions on both sides leading to the source and drain, and only the former portion is etched and the latter is not etched, but it is possible to form an effective channel with this type of transistor. Since it is the former that is formed, the advantages of removing surface defects and contamination can be fully obtained.

In addition, as a measure to prevent punch ^- through, as shown in FIG. Insulating layer 1
Groove type formed by depositing gate electrode 20 through 4
MOS transistors are also being considered. This type of transistor is similar to the transistor of the present invention in that the channel portion is recessed, but there is no channel doped region 12, that is, the punch-through prevention means is different, and a high impurity concentration is applied to the lower part of the gate electrode 20. A large mirror capacitance is formed because the source and drain regions are intruded, but
The difference is that in the device of the present invention, mirror capacitance occurs when a channel is formed, but such a capacitance does not exist in the off state when no channel is formed.

FIG. 4 shows an example of the manufacturing process of the device of the present invention.
Field oxide film 22 and channel cut 2 are selectively formed on p-type silicon substrate 10 by selective oxidation or other known appropriate methods to expose device formation regions.
4 and put it in the state shown in figure a. Next, the surface of the substrate in the element formation region is thermally oxidized to form an oxide film 26 of about 1000 Å thick, resulting in the state shown in FIG. Next, as shown in FIG. c, a resist 28 is applied and patterned to open a window W, and using this patterned resist film 28 as a mask, ions of p-type impurity such as boron are implanted to form a channel doped region 12. . Next, the resist is removed and thermal oxidation is performed to activate the ion implantation area, and as shown in Figure d, a gate oxide film 14 with a thickness of about 200 [Å] is formed.
make. This gate oxide film 14 digs into the surface of the exposed channel doped region 12 (as is well known, a thermal oxide layer is formed in a state where it digs in and bulges out half into the substrate and half into the outside of the substrate),
Further, since the thickness of the surrounding oxide film 26 increases to about 1100 Å, a depression is formed on the surface of the silicon substrate 10 even if the silicon substrate 10 is not etched. Mask alignment is performed using this depression as a mark, and the gate electrode 20 and gate oxide film 14 are patterned and the source and drain regions 16 and 18 are formed in the usual process as shown in FIG.

Although the silicon substrate is not etched in this manufacturing process (instead, the oxide film is etched), steps can be created by oxidation and the surface channel portion can be cleaned. Furthermore, compared to the oxide film 14 on the region 12 that becomes an effective channel, the oxide film on both sides of the channel is thicker, but this brings about the following advantages. That is, in FETs, when the gate oxide film is thinned, the gm increases and the short channel effect decreases, but on the other hand, even the slightest defects can cause accidents such as poor insulation of the gate electrode and short circuits. In this respect, the FET manufactured by the process shown in Fig. 4 has a thin gate oxide film thickness in the effective channel part, which has the advantage of large gm and little short channel effect. Because it connects to the thick gate oxide film (near the source and drain),
Insulation failure and short circuit accidents due to defects are less likely to occur.

As is clear from the above explanation, according to the present invention, alignment is easy, so short channels with fine patterns can be used.
It can form MOS transistors and is suitable for LSI etc. In addition, surface defects and contamination are removed in the step manufacturing process of the channel part, and the structure of the thin gate oxide film in the effective channel part and the thick gate oxide film on the source and drain sides allows for large gm, high breakdown voltage,
Advantages such as a small short channel effect can be obtained.

[Brief explanation of drawings]

FIGS. 1a and 1b are cross-sectional views explaining the structure of a conventional transistor with short channel effect prevention; FIGS. 2a and b are schematic cross-sectional views showing an embodiment of the present invention; and FIGS.
The figure is a cross-sectional view illustrating a transistor having another short channel effect prevention means, and FIGS. 4a to 4e are cross-sectional views showing an example of the manufacturing process of the transistor according to the present invention. In the drawing, 16 and 18 are source and drain regions, 1
0 is a substrate, 12 is a high impurity concentration region, and 20 is a gate electrode.

Claims (1)

[Claims] 1. A recess is provided in the center of the substrate surface between the source and drain regions, spaced apart from the source and drain regions, a high concentration impurity region of the same conductivity type as the substrate is formed in the recess, and the recess is formed on the substrate surface and on both sides thereof. An insulating layer is provided on the flat substrate surface extending to the source and drain regions of the recess, and a gate electrode is attached on the insulating layer to the recess and the flat region extending to the source and drain regions on both sides of the recess. The source and drain regions are formed thinly on the surface and thickly on the flat substrate surface on both sides of the recess, and the source and drain regions are formed so as to be separated from the insulating layer on the side surface of the recess through the substrate. characterized by becoming
MOS type field effect transistor. ”.