JPH0429242U

JPH0429242U -

Info

Publication number: JPH0429242U
Application number: JP6935690U
Authority: JP
Priority date: 1990-06-29
Filing date: 1990-06-29
Publication date: 1992-03-09
Anticipated expiration: 2005-06-29
Also published as: JP2536959Y2

Description

[Brief explanation of drawings]

第１図は、本考案に係る基準クロツク信号生成
装置の好適な実施例のシステムブロツク図、第２
図は、従来例の構成図である。１は基準クロツク信号生成装置、３は第１位相
比較器、５は第１低域通過フイルタ、７は第１電
圧制御発振器、９は第１分周器、１１は第２位相
比較器、１３は第２低域通過フイルタ、１５は第
２電圧制御発振器、１７は第２分周器、１９は第
１スイツチ回路、２１は第２スイツチ回路、Ａは
第１ＰＬＬ回路、Ｂは第２ＰＬＬ回路である。 FIG. 1 is a system block diagram of a preferred embodiment of the reference clock signal generation device according to the present invention;
The figure is a configuration diagram of a conventional example. 1 is a reference clock signal generating device, 3 is a first phase comparator, 5 is a first low-pass filter, 7 is a first voltage controlled oscillator, 9 is a first frequency divider, 11 is a second phase comparator, 13 is the second low-pass filter, 15 is the second voltage controlled oscillator, 17 is the second frequency divider, 19 is the first switch circuit, 21 is the second switch circuit, A is the first PLL circuit, and B is the second PLL circuit. be.

Claims

[Claims for Utility Model Registration] A first low-pass filter, a first voltage-controlled oscillator, and a first frequency divider are provided at the subsequent stage of the first transfer comparator to which an electric signal for generating a desired clock signal is input. a first PLL in which the frequency divider is arranged in this order, and the output signal of the first frequency divider is fed back to the first transfer comparator;
and a second transfer comparator into which the electric signal is input, a second low-pass filter, a second voltage controlled oscillator, and a second frequency divider are arranged in this order.
A PLL circuit is interposed before the first frequency divider, and the output signal of the first voltage controlled oscillator and the output signal of the second voltage controlled oscillator are switched and input to the first frequency divider. a first switch circuit capable of operating in synchronization with the first switch circuit and provided upstream of the second phase comparator;
In response to the output signal of the voltage controlled oscillator being input to the first frequency divider, the output signal of the second frequency divider is input to the second phase comparator, while the second voltage control a second switch capable of a switching operation for inputting the output signal of the first frequency divider to the second phase comparator in response to inputting the output signal of the oscillator to the first frequency divider; A reference clock signal generation device comprising: a circuit;