JPH0429277U - - Google Patents
Info
- Publication number
- JPH0429277U JPH0429277U JP1990069791U JP6979190U JPH0429277U JP H0429277 U JPH0429277 U JP H0429277U JP 1990069791 U JP1990069791 U JP 1990069791U JP 6979190 U JP6979190 U JP 6979190U JP H0429277 U JPH0429277 U JP H0429277U
- Authority
- JP
- Japan
- Prior art keywords
- intermediate frequency
- video
- video intermediate
- signal
- amplification circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 230000009977 dual effect Effects 0.000 claims description 2
- 230000003321 amplification Effects 0.000 claims 3
- 238000003199 nucleic acid amplification method Methods 0.000 claims 3
- 238000010897 surface acoustic wave method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 1
Description
第１図ないし第３図は本考案の映像処理回路の
１実施例を示し、第１図はブロツク図、第２図は
第１図の一部の結線図、第３図はアンテナ入力電
界強度に対する検波出力の特性図、第４図は従来
例の一部の結線図である。
２……テレビジヨンチユーナ、３……前置増幅
器、４……ＳＡＷフイルタ、６……ＶＩＦ増幅回
路、７……映像検波回路、８……ＩＦ・ＡＧＣ回
路、９……ＲＦ・ＡＧＣ回路、１０……ＡＧＣフ
イルタ、Ｑ２……デユアルゲートＭＯＳ型ＦＥＴ
、ｇ１，ｇ２……第１、第２ゲート。
1 to 3 show one embodiment of the video processing circuit of the present invention, FIG. 1 is a block diagram, FIG. 2 is a wiring diagram of a part of FIG. 1, and FIG. 3 is an antenna input electric field strength. FIG. 4 is a partial wiring diagram of a conventional example. 2... Television channel, 3... Preamplifier, 4... SAW filter, 6... VIF amplifier circuit, 7... Video detection circuit, 8... IF/AGC circuit, 9... RF/AGC circuit , 10...AGC filter, Q2 ...Dual gate MOS type FET
, g 1 , g 2 ...first and second gates.
Claims (1)
ユーナの映像中間周波信号を、前置増幅器、帯域
制限用の表面弾性波フイルタを介して映像中間周
波増幅回路に供給し、 前記映像中間周波増幅回路により、前記フイル
タの出力信号をＡＧＣ増幅して後段の検波回路に
供給する映像処理回路において、 前記前置増幅器として前記映像中間周波信号が
信号入力用の第１ゲートに供給されるデユアルゲ
ートＭＯＳ型ＦＥＴを設け、 前記映像中間周波増幅回路に供給されるＡＧＣ
電圧を前記ＦＥＴの利得制御用の第２ゲートに印
加する電圧印加手段を備えた映像処理回路。[Claims for Utility Model Registration] Supplying a video intermediate frequency signal of a television channel including a video carrier wave and an audio carrier wave to a video intermediate frequency amplification circuit via a preamplifier and a band limiting surface acoustic wave filter, In the video processing circuit, the video intermediate frequency amplification circuit AGC amplifies the output signal of the filter and supplies it to the subsequent detection circuit, the video intermediate frequency signal is supplied to a first gate for signal input as the preamplifier. A dual gate MOS type FET is provided to provide an AGC signal to be supplied to the video intermediate frequency amplification circuit.
An image processing circuit comprising voltage application means for applying a voltage to a second gate for gain control of the FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990069791U JPH0728781Y2 (en) | 1990-06-30 | 1990-06-30 | Video processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990069791U JPH0728781Y2 (en) | 1990-06-30 | 1990-06-30 | Video processing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0429277U true JPH0429277U (en) | 1992-03-09 |
| JPH0728781Y2 JPH0728781Y2 (en) | 1995-06-28 |
Family
ID=31605401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990069791U Expired - Lifetime JPH0728781Y2 (en) | 1990-06-30 | 1990-06-30 | Video processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0728781Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5536663U (en) * | 1978-08-31 | 1980-03-08 | ||
| JPH01106632A (en) * | 1987-10-20 | 1989-04-24 | Fujitsu General Ltd | Satellite television receiver tuner circuit |
-
1990
- 1990-06-30 JP JP1990069791U patent/JPH0728781Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5536663U (en) * | 1978-08-31 | 1980-03-08 | ||
| JPH01106632A (en) * | 1987-10-20 | 1989-04-24 | Fujitsu General Ltd | Satellite television receiver tuner circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0728781Y2 (en) | 1995-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0429277U (en) | ||
| JPH01269305A (en) | Semiconductor device | |
| JPH018032Y2 (en) | ||
| KR880002796Y1 (en) | Stereo recording device of video tape recorder | |
| KR860002768Y1 (en) | Mono signal driving circuit in stereo audio system | |
| JPS6316951B2 (en) | ||
| JPH0457928U (en) | ||
| JPH0356938Y2 (en) | ||
| JP2932104B2 (en) | FM receiver | |
| JPH0744132Y2 (en) | Video signal amplification circuit | |
| JP2517858Y2 (en) | VIF circuit such as television receiver | |
| KR900010828Y1 (en) | Audio signal muting circuit during telephone call | |
| JPS60139326U (en) | High frequency signal amplification circuit | |
| JPS6065634A (en) | Tuner device | |
| JPS6289830U (en) | ||
| JP2595412Y2 (en) | Envelope feedback circuit | |
| JPS584255Y2 (en) | television receiver | |
| JPS6096930A (en) | radio receiver | |
| JPS6213012U (en) | ||
| JPH02118373U (en) | ||
| JPS6157303U (en) | ||
| JPS61128817U (en) | ||
| JPS61140645U (en) | ||
| JPS6395316U (en) | ||
| JPS6352356U (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |