JPH0429331A - CCD solid-state image sensor - Google Patents

Abstract

PURPOSE:To improve S/N with simple constitution by equipping a source follower circuit which outputs the voltage signal held by a variable capacitor element to outside. CONSTITUTION:The output signal, which is transferred through a transmission gate MOSFET Q4, is transmitted to a variable capacitor element C2. This variable capacity element C2 is one whose capacitance changes by timing pulses psic, and constitutes am amplifying circuit which performs voltage amplification making use of the change of its capacitance. The maintenance voltage of the capacitor C2 as the variable capacitance element is sent out to an outside terminal OUT through the source follower output circuit consisting of an amplifying MOSFET Q5, through which it is transmitted to a gate, and a load MOSFET Q6, which is provided in a source. Thus, the substantial quantity of signals enlarges by the variable capacity element, and S/N improves.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a CCD (charge transfer device) solid-state image sensor, and relates to a technique that is effective for use in, for example, a CCD solid-state image sensor for increasing sensitivity.

[Conventional technology]

A floating diffusion amplifier (hereinafter simply referred to as FDA) is used as a charge-voltage conversion circuit and a voltage amplification circuit of a CCD solid-state image sensor. F like this,
Regarding D A, for example, U.S. Patent No. 4,646,1
There is No. 19.

[Problem to be solved by the invention]

When using the FDA as described above, the following two methods can be considered to increase the voltage gain.

■Reducing the capacitance value of the diffusion capacitor that receives the signal charge. ■
A source-grounded amplifier circuit with voltage gain is provided in the output circuit. However, method (2) has limitations due to the manufacturing process. ■
In the method described above, 1/f noise increases and no improvement in S/N can be expected.

An object of the present invention is to provide a CCD solid-state image pickup device with an improved S/N ratio using a simple configuration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a variable capacitance element is provided, which is charge-amplified by the output signal of a charge-voltage conversion circuit that receives signal charges output from the CCD transfer path and forms a voltage signal, and whose capacitance value is made smaller at the output timing than at the time of charge-up. Voltage amplification effect is performed.

[For production]

According to the above-mentioned means, since the substantial signal amount can be increased by the variable capacitance element, it is possible to improve the S/N ratio.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a CCD solid-state image sensor according to the present invention. Each circuit block and element in the figure is formed on a single semiconductor substrate such as single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The CCD solid-state image sensor of this example has an interline C
It is aimed at CD-type solid-state imaging devices, and the imaging array consists of a photodiode and a vertical COD (charge phase device). Here, the accumulated and transferred signal charges are serially outputted through a horizontal CCD that functions as a horizontal transfer shift register. This signal charge is transferred by the transfer pulse φ
. The signal is provided in the output section and transmitted to the output capacitor C1 in synchronization with . The signal charge is converted into a voltage signal by this capacitor C1, amplified by a preamplifier PA as described below, and outputted from an external terminal OUT.

The preamplifier PA is composed of the following circuit. The reset MOSFET QI is switch-controlled by the reset pulse φ7, and is turned on at the timing when the reset pulse φ7 is set to high level to apply the reset voltage VB to the output capacitor C1.

The amplifying MOSFET Q2 whose gate is supplied with the holding voltage of the output capacitor C1 and the load MOSFET Q3 provided at its source constitute a first-stage source follower circuit. The output signal of this first stage source follower circuit is
The signal is transmitted to the next circuit through the transmission gate 1-M03FETQ4 which is switch-controlled by the transfer timing pulse φ6. The output signal transferred via the transmission gate MOSFET Q4 is transmitted to the variable capacitance element C2. This variable capacitance element C2 receives a timing pulse φ. It is a variable capacitance element whose capacitance value changes due to the change in capacitance value, and constitutes an amplifier circuit that performs a voltage amplification effect using the change in the capacitance value.

The voltage held by the capacitor C2 as the variable capacitance element is sent to the external terminal 0tJT through a source follower output circuit consisting of an amplifying MOSFET Q5, which is transmitted to the gate, and a load MOSFET Q6, which is provided to the source.

FIG. 2 shows a schematic cross-sectional view of the element structure of one embodiment of the variable capacitance element C2.

A MOS capacitor is used as the variable capacitance element C2 in this embodiment. That is, a gate capacitance is formed between the gate electrode as one electrode and the substrate P using a thin gate oxide film (not shown) as a dielectric. Then, an N'' layer is formed so as to overlap with the end of the gate electrode, and this layer is used as a control electrode to supply a timing pulse φ. Or, it is the same as when the drain is omitted.

The outline of the operation of this variable capacitance element is as follows. When the timing pulse φ is at a high level, the potential of the N'' layer, which is equivalent to the source region, is equal to or higher than the signal voltage applied to the gate electrode, so a channel is not formed under the gate electrode and depletion occurs. At this time, the capacitance value of the capacitive element is the combination of the MOS capacitor, which has a relatively large capacitance with the gate insulating film as the dielectric, and the N'' layer and substrate P, with the depletion layer as the dielectric. The junction capacitance between them is connected in series, and the combined capacitance becomes a small capacitance value.

When the timing pulse φゎ is at a low level, the potential of the N'' layer, which is equivalent to the source region, becomes lower than the threshold voltage with respect to the signal voltage applied to the gate electrode, so there is a dotted line under the gate electrode. A channel as shown in is formed.At this time, it has a large capacitance value consisting of a MOS capacitor using the gate insulating film as a dielectric.

FIG. 3 shows a schematic cross-sectional view of the element structure of another embodiment of the variable capacitance element. The variable capacitance element of this embodiment uses a PN junction capacitor in which a control terminal and a capacitor electrode are shared. That is, when a high voltage is applied to the N1 layer by the timing pulse φ, the depletion layer shown by the dotted line in the figure expands, and the capacitance value decreases. On the other hand, when a low voltage is applied to the N' layer by the timing pulse φC, the depletion layer shown by the dotted line in the figure becomes narrower and the capacitance value changes to a larger value.

FIG. 4 shows an example of an operation waveform diagram for explaining the signal output operation when the variable capacitance element shown in FIG. 2 is used.

During the reset period, the timing pulses φ and φ become high level, and the reset level of the output capacitor C1 is sent out from the output terminal OUT.

At this time, when the timing pulse φG becomes high level and the reset level voltage is charged and amplified in the capacitor C2, the timing pulse φ becomes low level. Therefore, charge amplification to the capacitor C2 is performed when the capacitance value is relatively large. Here, the voltage C2A indicated by the dashed line is the threshold voltage of the capacitor C2.

Output transfer pulse φ. Similarly, when the signal charge is transferred to the output capacitor C1 due to the high level, the timing pulse φ6 is set to the high level again in order to output the signal charge. At this time as well, the timing pulse φ becomes low level in the same manner as described above, making the capacitance value of the capacitor C2 relatively large.

Then, during the period when the timing pulse φ6 is at a low level and the transmission gate 1-M03FETQ4 is in the off state,
Timing pulse φ. As C2 becomes high level and a depletion layer is formed under the gate electrode constituting the capacitor C2, its capacitance value is changed to a small value.

Although the capacitance value of the capacitor C2 changes small in this way, the amount of charge corresponding to the reset level and signal level is constant. Therefore, transmission game) MO
The holding voltage of capacitor C2 in the hold state where SFET Q4 is turned off increases as the capacitance value C decreases from the relational expression: ■(voltage) - 〇(charge amount)/C(capacitance value). do. In other words, the signal voltage is amplified.

The reset level and signal voltage amplified by this capacitor C2 are applied to the source follower output MOSFET Q5.
It is output from the external terminal OUT through Q6. The reason for adopting this method of outputting the reset level in addition to the signal voltage is to take into consideration the provision of a correlated double sampling circuit in the external circuit.

Note that the output MOSFETQ5 is connected to the variable capacitance element C2.
The gate capacitance of MOSFET Q4 and the source and drain capacitances on the output side of MOSFET Q4 are connected in parallel. Therefore, the actual amplification action is performed in response to a change in the combined capacitance value obtained by adding the above-mentioned parasitic capacitance to the above-mentioned change in the capacitance value of the capacitor C2. Therefore, in order to increase the amplification factor, it is necessary to design such that the parasitic capacitance value such as the gate capacitance of the output MO5FET becomes small with respect to the change in the capacitance value of the capacitor C2. In addition, since the amplification effect is performed by the variable capacitance element C2 as described above, the 1/f
No noise is generated, making it possible to reduce noise.

The effects obtained from the above examples are as follows. That is, +1) A variable capacitance element that is charge-amplified by the output signal of a charge-voltage conversion circuit that receives signal charges output from the CCD transfer path and forms a voltage signal, and whose capacitance value is smaller than that of the charge amplification at the output timing. By providing a voltage amplification function, the substantial signal amount can be increased, and the S/N ratio can be improved.

(2) By using a MOS capacitor as a variable capacitance element, it is possible to obtain an effect that 1/f noise is not generated and an amplification effect with good linearity can be performed.

Although the invention made by the inventor of the present application has been specifically explained based on examples, it goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof. Nor. For example, the variable capacitance element may be any element whose capacitance value changes according to a timing pulse. Further, the imaging array may be an interline type COD as in the embodiment described above, or may be a CCD type solid-state image sensor that employs another readout method. Also, C
The CD solid-state image sensor may constitute a line sensor in addition to the area sensor as in the above embodiment.

This invention can be widely used in CCD solid-state imaging devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a variable capacitance element is provided, which is charged up by the output signal of a charge-voltage conversion circuit that receives signal charges output from the CCD transfer path and forms a voltage signal, and whose capacitance value is made smaller at the output timing than at the time of charge-up. By performing the voltage amplification operation, the substantial signal amount can be increased with a simple configuration, so that the S/N ratio can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a CCD solid-state image sensor according to the present invention, FIG. 2 is a schematic cross-sectional view of an element structure showing an embodiment of a variable capacitance element used therein, and FIG. FIG. 4, which is a schematic cross-sectional view of the element structure showing another embodiment of the variable capacitance element used therein, is a waveform diagram for explaining an example of the operation of the CCD solid-state image sensor according to the present invention. PA...Preamplifier, CI...output capacitor, signal level before signal level

Claims (1)

[Claims] 1. A charge-voltage conversion circuit that receives signal charges output from a CCD transfer path and forms a voltage signal, and a charge-voltage conversion circuit that is charged up via a switch element by the output signal of this charge-voltage conversion circuit and output. A CCD solid-state imaging device comprising: a variable capacitance element whose capacitance value is made smaller at timing than when charging up; and a source follower output circuit that outputs a voltage signal held in the variable capacitance element to the outside. . 2. The CC according to claim 1, wherein the variable capacitance element utilizes a MOS capacitance.
D solid-state image sensor.