JPH0418737A - CCD solid-state image sensor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a CCD (charge transfer device) solid-state image sensor, and relates to a technique that is effective for use in, for example, a CCD solid-state image sensor for increasing sensitivity.

[Conventional technology]

A solid-state imaging camera using a CCD solid-state imaging device is provided with a correlated double sampling circuit (CDS circuit). As a result, the output circuit that converts the signal charge into a voltage signal removes the cent noise and the 1/f noise. For such a correlated double sampling circuit,
February 1974, IEE Journal Off゛Solid-Stay I Zakisotsu 5C-9,1
, 1-13 (IFI':HJ, of 5olid-3t
ate C1rcuits).

[Problem to be solved by the invention]

The above-mentioned correlated double sampling circuit is provided as an external circuit of the CCD solid-state image sensor. Therefore, the inventor of the present application considered incorporating a correlated double sampling circuit. In this case, since the correlation-multiplexing circuit itself has no voltage gain, there is a limit to the S/N ratio. In particular, in a solid-state image sensor that has a large number of pixels in order to improve image quality, the S/N ratio deteriorates because the amount of readout charge decreases as the device becomes smaller.

The purpose of this invention is to improve CC1 with improved S/N.
An object of the present invention is to provide a solid-state image sensor.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Failure to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In addition to incorporating a correlated double sampling circuit, a variable capacitance element is used as a capacitor that holds the output signal passed through this correlated double sampling circuit, and its capacitance value is smaller during output timing than during charge-up. voltage amplification effect.

[For production]

According to the above-mentioned means, since the external circuit can be simplified by incorporating the correlated double sampling circuit, and the actual signal amount can be increased by the variable capacitance element, the S/
It becomes possible to improve N.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a CCD solid-state image sensor according to the present invention. Each circuit block and element in the figure is formed on a single semiconductor substrate such as academic silicon using known semiconductor integrated circuit manufacturing techniques.

The CCI) solid-state image sensor of this embodiment is an interline CCD type solid-state image sensor 7-1. : The imaging array is perpendicular to the fumetodiode (C0D (charge phase device)).
It consists of Here, the accumulated and transferred signal charge is transferred to the horizontal CCD which acts as a horizontal transfer shift register.
output serially through This signal charge is converted into a voltage signal by an output capacitor (not shown) provided at the output section, and the signal charge is converted into a voltage signal by an output capacitor (not shown) provided at the output section, and the preamplifier (amplifier circuit) PA
is amplified by

The preamplifier PA is constructed by the following circuit surrounded by a dotted line in the figure. Liseso I・M OS F Ei”
QI is switch-controlled by a reset pulse φ□·, and turns on at the timing when it is set to high level, thereby applying a reset voltage VB to the output capacitor. The amplification MOSFETQ2 whose gate is supplied with the holding voltage of the output capacitor and the load MOSFETQ3 whose source is numbered constitute a first-stage source follower circuit. The output signal of this first stage source follower circuit is outputted to the next stage through a second stage source follower output circuit consisting of a MOSFET Q 5 and a load MOSFET Q 6 provided at its source.

The following double sampling circuit and output amplification circuit are provided for such an interline CCD type solid-state image sensor f.

The output signal of the preamplifier I)A is transmitted to one electrode of the capacitor CI. A reset pulse φ is connected between the other electrode of this capacitor CI and the ground potential point of the circuit.
6 is provided. The signal on the other electrode of the capacitor C1 is a transfer timing pulse φ. The transmission signal is transmitted to the variable capacitance element C2 via the MOSFET Q8. -Above capacitor C1 and reseno1-M03FET
Q7 constitutes a substantial correlated double summing circuit CDS. The two-legged variable capacitance element C2 is a variable capacitance element whose capacitance value changes according to the timing pulse φ,
An amplifier circuit A MP is constructed which performs a voltage amplification effect using the change in the capacitance value.

1-The holding voltage of the capacitor C2 as a variable capacitive element is transmitted to the gate of the amplifying MOSFE TQ
The signal is sent to an external terminal OUT through an output circuit OB consisting of a load MO8FETQIO and a load MO8FETQIO provided at the source.

FIG. 2 shows a schematic cross-sectional view of the element structure of an embodiment of the upper rotational transformation element C2.

The variable capacitance element C2 of this embodiment uses a MOS capacitor. That is, a gate capacitance is formed between the D1- electrode and the substrate P using a thin gate oxide film (not shown) as a dielectric, using the D1- electrode as the -. side electrode. Then, an N layer is formed so as to overlap with the end of the gate electrode.
This is used as a control electrode and a -ζ timing pulse φ is supplied. This structure is similar to a MOS FET in which one of the sources and drains is omitted.

The outline of the operation of this variable capacitance element is as follows. When the timing pulse φ is at a high level, the potential of the N layer equivalent to the source region is equal to or higher than the signal voltage applied to the gate electrode, so there is a channel under the gate electrode. It is not formed and a depletion layer is formed.

At this time, the capacitance value of the capacitive element is the junction capacitance between the MOS capacitor, which has a relatively large capacitance value with the gate insulating film as the dielectric, and the N layer and substrate P, with the depletion layer as the dielectric. are connected in series, and the combined capacitance has a small capacitance value.

When the timing pulse φ is at low level, the potential of the N layer equivalent to the source region becomes lower than the threshold voltage with respect to the signal voltage applied to the gate electrode, so there is a dotted line below the gate electrode. A channel as shown in is formed. At this time, a large capacitance value is obtained, which is composed of a MOS capacitor using the gate insulating film as a dielectric.

FIG. 3 shows a schematic cross-sectional view of the element structure of another embodiment of the variable capacitance element. The variable capacitance element of this embodiment uses a PN junction capacitor in which the control terminal r and the electrode of the capacitor are shared. That is, the timing pulse ψ. Therefore, when a high voltage is applied to the N layer, the depletion layer shown by the dotted line in the figure expands and the capacitance value becomes smaller. On the other hand, when a low voltage is applied to the N'' layer by the timing pulse φ, the depletion layer shown by the dotted line in the figure becomes narrower, and the capacitance value changes to a larger value.

FIG. 4 shows an example of an operation waveform diagram for explaining the signal output operation when the variable capacitance element shown in FIG. 2 is used. The operation of the circuit shown in FIG. 1 will be described below with reference to the same figure.

The reset level and the output level are alternately output from the preamplifier PA in synchronization with the timing pulse φ6 of the preamplifier PA.

Timing pulses φ8 and φG for correlated double sampling are generated in synchronization with the output signal as described above. That is, the timing pulse φ7 changes to a high level after the output signal of the preamplifier PA is set to a set level, and changes to a low level before being set to an output level corresponding to a read signal from the preamplifier PA. When the timing pulse φ6 is used, the output signal of the preamplifier PA changes from the output level to the high level, and the output signal of the preamplifier PA changes to the high level.
The read signal from A changes to low level before being set to reset level.

Since the timing pulse φR becomes high level at the timing when the reset level is output from the preamplifier PA,
MOSFET Q7 is turned on and a reset level is accumulated in capacitor CI. Next, the above MOSFE
After TQ7 is turned off, the preamplifier PA outputs an output level corresponding to the read charge. As a result, an output level based on the reset level is output through the capacitor C1. This signal is Mo 3 F turned on by timing pulse φ6.
It is transmitted to capacitor C2 through E i''Q8.

At this time, the capacitor C2 is connected to the evening timing pulse φ6.
The timing pulse φ before becomes high level. It is made to have a relatively large capacitance value in response to being set to a low level. "The change of the double timing pulse φ to high level turns on the MOS FET Q8, and the capacitor C2, which has a relatively large capacitance value, is charged up by the output level through the capacitor CI. will be done. After this signal transfer is performed, the timing pulse φ is applied. Each time MO8FETQ8 is set to low level, MO8FETQ8 is turned off, and the timing pulse φ changes from low level to high level. As a result, 1. The capacitance value of the capacitor C2 changes to a small value in accordance with the formation of a depletion layer under the gate electrode. Here, the voltage CVT shown by the - dotted chain line is the threshold voltage of the capacitor C2.

In this way, while the capacitance value of the capacitor C2 forming the amplifier circuit in the correlated double sampling circuit changes small, the amount of charge is constant. Therefore, ζ, the holding voltage V in the amplification capacitor c2 increases as the capacitance value C becomes smaller, according to the relational expression (2) (voltage) = Q (amount of charge)/C (capacitance value). In other words, the signal voltage is amplified.

The signal voltage amplified by each capacitor C2 is passed through the source follower output MOSFET Q9 to the external terminal OU.
Output from T.

Note that the output MOSFE 'l for the variable capacitance element C2
” The gate capacitance of Q8 and the source and drain capacitances on the output side of MOSFET Q8 are connected in parallel. Therefore, the actual amplification effect depends on the change in the capacitance value of capacitor C2 as described above and the parasitic effects as described above. This is done in response to a change in the combined capacitance value including the capacitance.For this reason, in order to increase the amplification factor, the output MOS F
It is necessary to design the ET so that the parasitic capacitance value of the gate capacitance etc. is small. Further, since the amplification effect is performed by the variable capacitance element as described above, I/f noise unlike in a source-grounded amplifier circuit is not generated, and noise can be reduced.

The effects obtained from the above examples are as follows. That is, (1) In addition to incorporating a correlated double sampling circuit, as a -1-capacitor that constitutes a circuit that amplifies the output signal through this correlated double sampling circuit, the capacitance value is smaller at the output timing than at the time of charge-up. By providing a variable capacitance element to perform a voltage amplification effect, it is possible to simplify the external circuit by incorporating a correlated double zumbling circuit, and the variable capacitance element constituting the amplification circuit allows the substantial signal to be amplified. Because the amount can be increased S/
This has the effect that N can be improved.

(Using a MOS capacitor as a 2-in variable capacitance element has the effect that 1./f noise does not occur and a voltage amplification action with good linearity can be performed.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. For example, a correlated double sampling circuit uses a capacitor and a switch MO as described above.
Although the present invention is constructed by combining the S FET with SFET, various embodiments may be adopted, such as providing a buffer amplifier on the output side of the capacitor CI in order to increase the speed. Further, the variable capacitance element may be any element whose capacitance value changes according to a timing pulse.

Further, the imaging array may be an interline type CCD as in the embodiment described above, or may be a CCI) type solid-state imaging device that employs another readout method. Further, the CC11) solid-state image sensor may constitute a line sensor other than the area sensor as in the above embodiment.

This invention can be widely used in CCD solid-state imaging devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, in addition to incorporating a correlated double sampling circuit, a variable capacitance element whose capacitance value is smaller at output timing than at charge-up time is used as a capacitor that constitutes a circuit that amplifies the output signal through this correlated double sampling circuit. By incorporating the correlated double sampling circuit and performing voltage amplification, the external circuit can be simplified, and the actual signal amount can be increased by the variable capacitance element that makes up the amplifier circuit.
/N can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a CCD solid-state image sensor according to the present invention, FIG. 2 is a schematic cross-sectional view of an element structure showing an embodiment of a variable capacitance element used therein, and FIG. FIG. 4, which is a schematic cross-sectional view of the element structure showing another embodiment of the variable capacitance element used therein, is a waveform diagram for explaining an example of the operation of the CCD solid-state image sensor according to the present invention. PA...preamplifier, CDS...correlated double zumbling circuit, 8MP...amplifier circuit, OB...output circuit.

Claims (1)

[Claims] 1. An amplifier circuit that receives a signal charge output from a CCD transfer path and forms a voltage signal, a correlated double sampling circuit that receives an output signal of the amplifier circuit, and a correlated double sampling circuit that receives the output signal of the amplifier circuit. It is equipped with a variable capacitance element that is charged up by an output signal passed through the capacitor, and whose capacitance value is made smaller at the output timing than when charging up, and a source follower output circuit that outputs the voltage signal held in this variable capacitance element to the outside. A CCD solid-state image sensor characterized by: 2. The CC according to claim 1, wherein the variable capacitance element utilizes a MOS capacitance.
D solid-state image sensor.