JPH042971B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a readable and writable storage device for storing display data.

Conventionally, microcomputers that have a display drive circuit built into their chip have used a built-in RAM (random access memory) or part of a register as a display area. Necessary data is transferred from this display area to a data store circuit for display, and the display element is driven by a display driver. Or read out necessary data from the display area and change the display data. FIG. 1 shows an example of a conventional display driver circuit. RAM 5 with a storage capacity of 2 ⁿ × 2 ^m bits is used to hold internal data.
An n-bit X register 4 outputting an X address signal 3 and a Y address signal 2 for addressing
It is equipped with an m-bit Y register 1 that outputs . The output of the RAM 5 is coupled to an accumulator 7 via a bus 6 having an 1-bit configuration. Further, the display circuit serially transfers data from the accumulator to the shift register 9, and inputs the data from the parallel output 10 to the driver 12, and the output of the driver 12 drives the display device 13 by the drive output 11. A part of the RAM 5 is used as a storage circuit for display data, and each time data is transferred from the RAM 5 to the shift register by software via the accumulator 7 in response to a transfer command. Liquid crystals, light emitting diodes, and fluorescent displays are commonly used as display devices, and a dynamic drive system is used to efficiently drive multiple segments with a small number of pins. For example, to drive 128 segments, use a matrix of 8 timing signals and 16 data signals at 1/8 duty. The problem at this time is that if one cycle of display duty is 8 msec, data transfer must be performed once every 1 msec, that is, 1/8 of 8 msec. This timing is shown in Figure 2. If To is the period for rewriting data once, that is, 1 msec, and the time for rewriting data is TDT, in order to rewrite data once in this system, the address setting of RAM, that is, X register 4, Y The register 1 is set, the data in the RAM is transferred to the accumulator 7, and from there to the shift register 9. When this is repeated several times (for example, 4 times if the data is 4 bits parallel in a 16-bit shift register), rewriting of the drive data is completed. In this case, as shown in FIG. 2, the processing time required to rewrite the data is too long, resulting in a serious drawback in that the original processing time of the microcomputer is reduced. Furthermore, if processing during the remaining time after data rewriting does not fall neatly within To, To will fluctuate, causing unevenness in the brightness of the display device.

The present invention eliminates these drawbacks, and therefore, an object of the present invention is to provide a system that can automatically send necessary data to a display device without having to transfer the display data each time using software, thereby improving the performance of a microcomputer. The goal is to make sure that enough time is available for software processing without being bothered by the display, and to eliminate fluctuations in the brightness and flickering of the display device.

FIG. 3 shows in block diagram form one embodiment of the system of the present invention. RAM17 is Y register 15 and X
In addition to reading or writing the contents of the cell whose address is specified by the contents of the register 16 via the bus line 25, there is also a store circuit 18 for display.
can be read directly without going through the bus line. At this time, due to the action of the timer 19, the X address specified by the necessary signal 23 is changed once when necessary to the signal 2.
6, it is separated from the X data 22 and selected. At this time, 1 bit specified by the RAM address corresponds to 1 segment of the display 1:1.
Correspond with this. In other words, for 128 segments, this
Display information is stored in 128 bits of RAM 17. Therefore, it corresponds to segments that require data rewriting.
Data rewriting is completed by simply rewriting the RAM bit data. In addition, the display data can be read out in exactly the same way as before, and as a result, compared to the conventional method, the software does not need to be concerned with the transfer of display data at all, so there is no burden on the software, and the program area can be saved. It becomes possible to simplify the program.

FIG. 4 is a more specific example of the circuit shown in FIG. 3. The Y data is input to the Y register 34, and further converted into 2 ^m CAS signals by the Y decoder 33.
A circuit 30 that performs read/write control and data multiplexing is connected to data lines 51 and 5.
2 on bus line 45 or read.
RAM consists of cells of 2 ⁿ × 2 ^m × 4 bits, where 2 ⁿ ′ × 2 ^m × 4 bits are for the display area, and 2 ⁽ⁿⁿ ′ ⁾ × 2 ^m × 4 bits are for the normal memory. This will be a working area. The X data enters the X register 36 and then directly goes to the X decoder 3.
5 is a working area of 2 ⁽ⁿⁿ ′ ⁾ × 2 ^m × 4 bits, and a display area of 2 ⁿ ′ × 2 ⁿ × 4 bits is input by the multiplexer 38 to the signal from the X register or from the timer. One of the signals is selected and inputted to the _XD decoder 37. timer 3
9 has a function of generating a time division signal for dynamic drive of the display, and a frequency divider 40 divides the time division signal and outputs a signal for selecting a RAM address. The signal is sent to the multiplexer 38 to select the X address of the RAM for outputting the data to be input into the 43. The differentiator 41 generates a multiplex signal 57 to indicate that it is time to replace the data in the latch 43 in order to set the display data to the next timing by the timer 39.

Only at this time, the X _D decoder selects the address set by the frequency divider 40 instead of the X data. 4
2 further narrows the width of signal 57 to generate a strobe signal for latching. FIG. 7 shows this situation. Display selection signal is signal 57
Also, the latch strobe signal corresponds to signal 56. The X address is switched to a signal on the timer side only when the display is selected. The latch 43 transfers data from RAMs 31 and 32 to signals 51 and 5.
2, and all signals are input to the latch 43 in parallel without multiplexing, and are further input to the display driver 44 in parallel.
is input. As a result, you can read and write all areas of the RAM working area and display area completely freely most of the time, and at the same time, the data in the display area can be sequentially latched only by hardware using a timer.
The data is sent to the dynamic drive and becomes time-division data. At this time, if you are having trouble reading or writing the RAM while reading the display area to the latch side, as shown in Figure 4.
If you output it as a WAIT signal and wait for one instruction only during this period, there will be no problem.

Figure 5 is intended to make the present invention more understandable.
This is a specific example of one bit in the Y direction of RAM. In the figure, m is the number of bits in the Y register 34, and n and n' are numerical values each indicating the number of bits in the X register 36, each of which corresponds to a specific storage area in the RAM. When input data DI is write enable WE, tri-state inverter 61,
Y address selected via 62, i.e.
A BIT line is connected to the row in which one of CAS ₁ to CAS ₂ ^m is selected and transistors 64 and 65 are turned on.
It is input via the line. This data is
The cells of one selected column of RAS _1-2 ⁽ⁿⁿ ' ⁾ or _RAS'1-2 ⁿ ' are written. Cells 71 to 73 and cells 74 to 75 each correspond to one bit of the RAM cell, and the written data is sent to the inverter 63 as an amplifier via the Y address selected by CAS _{1 to 2} ^m , and output data D ₀ becomes. At the same time, the BIT line is directly input to the data terminal of latch 69 using inverter 68 as an amplifier. Therefore, in FIG. 4, transistors 64, 65 and inverters 60-63 correspond to control circuit 30, one bit of latch 43 corresponds to latch 69, and one bit of driver 44 corresponds to driver 70. When the timer requests rewriting of the drive data and selects one of RAS' ₁ to RAS' ₂ ⁿ ', the data in the inverter 68 becomes valid at this time, so the latch strobe signal STB is input at the same time. Data is latch 6
9 is stored. If the BIT line and the signal DRAM-EN that separates the line are divided into the working area and display area on the software, they can be separated by transistors 66 and 67, and the latch 69 can be read and written to the working area and triggered by the timer. This is convenient because the strobes can be performed at the same time, and the rate at which the wait signal is applied can be drastically reduced.

FIG. 6 shows another embodiment of the present invention, in which a RAM working area 81 and a display area 82 are shown.
The division is performed in the X direction, and the output of the register and decoder for selecting the X address is input to the data control and multiplex circuit 80. On the one hand, X data is working area 81
is input to the decoder 84. Also, on the display area 82 side, the X data is multiplexed with the signal of the timer 88 as in FIG. 4, and is selected by the decoder 87. Therefore, the signal in the display area 82 is
m' bits enter latch 85 in parallel and are further input to driver 86.

According to the present invention, since the proportion of time that the storage circuit spends on reading and accessing display data is reduced, more accesses can be made in the remaining time, increasing the degree of freedom in accessing the storage circuit. Furthermore, since display data is reliably supplied from the latch circuit to the driver, the display quality is also good.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional storage device. FIG. 2 is a diagram showing the operation timing of FIG. 1. FIG. 3 is a diagram showing an embodiment of the storage device of the present invention. FIG. 4 is a diagram showing a specific example of FIG. 3. FIG. 5 is a diagram showing a specific example of the RAM portion of FIG. 4. FIG. 6 is a diagram showing another embodiment of the storage device of the present invention. FIG. 7 is a diagram showing the operation timing of the embodiment of FIG. 4. 30...Write control and data multiplexer, 38...multiplexer, 40...
... Frequency divider, 41 ... Differential signal generator, 42 ... Strobe signal generator, 31, 81 ... RAM working area, 32, 82 ... RAM display area, 71 to 75 ... RAM cell 1
Bit minute.

Claims (1)

[Scope of Claims] 1. In a storage device having a memory circuit for storing display data whose address is selected by a first address signal and to be displayed by a display driver, a circuit for generating a time division signal; and a circuit for generating a time division signal; means for dividing the frequency of a signal to form a second address signal; means for forming an address switching signal when reading the display data; and a period for inputting the address switching signal is at least one of the first address signals. address switching means for supplying the second address signal for selecting an address of the memory circuit instead of the memory circuit; A storage device comprising: a holding circuit that latches the display data selected and read from the storage circuit and supplies the display data to the display driver.