JPH042980B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer system between multiple data processing devices connected in parallel to a single common bus.

FIG. 1 is a conventionally used data processing system having a single common bus. In FIG. 1, 101 is a single common bus, 102 is a central processing unit (hereinafter abbreviated as CPU), 103 is an input/output device (hereinafter abbreviated as IOC), and 104 is a storage device (hereinafter abbreviated as memory). In such a data processing system having a single common bus configuration, the response speed (that is, the time from receiving a data request to sending back the requested data) of each data processing device constituting the system varies. Since all such data processing devices are connected to a single common bus, an efficient data transfer method is desired.

There are two types of data transfer methods based on the direction of transfer. One type is called input transfer, which involves one requesting device (10 in Figure 1).
2, 103, 104) requests the other party's device (the other one of 102, 103, 104 in FIG. 1) to transfer predetermined data of the other party's device. It is something to do. For example, when reading from a memory, an address is first transferred from the requesting device to the memory, which is the other device, and then read data is transferred from the memory to the requesting device. In other words, input transfer consists of transfer in two directions, considering the direction of transfer. On the other hand, there is something called output transfer. For example, in a transfer such as a memory write request, write data is only transferred from the requesting device to the memory, and the transfer is performed only once in one direction.

Conventionally, either an interlock transfer method or a split transfer method has been used as an input transfer method.

FIG. 2 is an example showing the split transfer method. In FIG. 2, BSBUSY-00 is a signal indicating the bus occupancy state. Note that the plus and minus signs in the signal name are "+", and if a logically significant state is a logic value "1", the voltage level H (High) is a logic value "1". ”, and if it is a negative sign “-”, a significant state is represented by a logic value “0” and a voltage level L (LOW).

A device that wishes to perform transfer using the bus issues a request to use the bus. A prioritization mechanism (connected to the single common bus, not shown in FIG. 1) determines bus contention and provides control for awarding use of the bus to only one data processing device. conduct. When the device desiring to perform the above transfer is given the right to use the bus by the priority determination mechanism, it sets the bus occupancy display signal BSBUSY-00 to a logical value of “0”, that is, L.
level. The device that has been granted the right to use the bus sets the transfer display signal BSDVLD-00 to a logical value of “0”.
That is, the signal is set to L level and transfer via the bus is started. Address ADDRESS, data DATA, and control signals are transferred in synchronization with transfer display signal BSDVLD-00. Now, if this transfer is a memory read request, the read request address is transferred to the memory. The other device that received the transferred data sets the acknowledgment signal BSACEP-00 to a logical value of “0”.
That is, it is set to L level and notifies the requesting device that the transfer data has been received. This acknowledgment signal
The requesting device that receives BSACEP-00 returns the transfer display signal BSDVLD-00 to the logical value "1", that is, the H level. The other party's device that receives this transfer indication signal BSDVLD-00 sends an acknowledgment signal BSACEP-
00 is returned to the logic value "1", that is, the H level. This completes the transfer of the request from the requesting device to the other party's device.

A feature of the split transfer method is that when the transfer of the request from the requesting device to the other device is completed, the requesting device relinquishes possession of the bus, as shown at point a in FIG. The requesting device that has relinquished the exclusive right to the bus waits for the requested data to be transferred from the other device.

When the other device is ready to transfer the requested data, it issues a bus use request and
When the right to use the bus is granted as shown by the dot, the requested data is sent out in synchronization with the transfer display signal BSDVLD-00. The requesting device that has received the requested data uses the acknowledgment signal BSACEP-00 to notify the other device that it has received the transferred data. The other party's device that receives this notification sends a transfer indication signal.
The transfer is terminated by returning BSDVLD-00 to the logical value "1", that is, the H level.

In contrast, an interlock transfer method is shown in FIG. In FIG. 3, indicates a period during which a request is transferred from the requesting device to the other party's device, and indicates a period during which the other party's device transfers requested data to the requesting device. These and transfer display signals
Regarding the BSDVLD-00 and the acquisition response signal BSACEP-00, they are the same as the split transfer method already described in FIG. 2. However, the interlock transfer method uses the bus occupancy display signal BSBUSY-00 in Figure 3.
As is clear from the above, the feature is that the requesting device does not relinquish the right to occupy the bus.

Comparing the interlock transfer method and the split transfer method based on FIG. 2 and FIG.
In the meantime, other devices can use the bus to perform transfers, increasing the probability that devices connected to the bus can use the bus compared to interlock transfers. On the other hand, in the split transfer method, in devices where the time between a and b is short, there is a loss in time between when the other device issues a bus use request to transfer the requested data and when the right to use the bus is granted. There is. Furthermore, if another transfer occurs between a and b, there is a drawback that the arrival of the requested data at the requesting device is delayed until that transfer is completed. This appears to the requesting device as a delay in access time when reading from memory.

The purpose of the present invention is to use interlock transfer for devices that require a short time from receiving a request to sending back the requested data, and to use the split transfer method for devices that require a relatively long time. The purpose is to improve bus transfer efficiency by taking advantage of the characteristics of each transfer method.

According to the present invention, the present invention includes a plurality of data processing devices connected in parallel to a single common bus, and a first data processing device of one of the plurality of data processing devices is one of the plurality of data processing devices. , another second
In the data transfer method, the second data processing device sends a data request to the first data processing device and transfers the requested data.
If the data processing device is a device that takes a short time from receiving a data request from the first data processing device to sending back the requested data, the response in the first mode is a device that takes a relatively long time. In some cases, the second mode response is performed, and if the first mode response is performed, the first data processing device continues to perform the first mode response even after receiving the first mode response. A first mode of data transfer is performed in which the second data processing device continues to hold the bus occupancy and relinquishes the bus occupancy when the second data processing device receives the transferred request data; If the second mode response is received, the first data processing device relinquishes the exclusive right to the bus upon receiving the second mode response, and the second data processing device provides a data transfer method characterized in that a second mode of data transfer is performed in which the right to occupy the bus is newly secured and requested data is transferred to the first data processing device. It will be done.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 4 shows the main parts of a bus interface circuit in a data processing device according to an embodiment of the present invention, and FIGS. 5 and 6 are time charts thereof.

In FIG. 4, 1 to 3, 26, and 27 are bus drivers having an inverter function, and 4 to 8 are bus receivers having an inverter function.
BSBUSY-00 is a bus occupancy display signal that indicates that the bus is occupied, BSDVLD-00 is a transfer display signal that indicates that transfer data is loaded on the bus, and BSACEP-00 is a bus occupancy display signal that indicates that the bus is occupied. This is an acknowledgment signal indicating an acknowledgment of the handshake of the transfer data receiving device in response to the signal, and is respectively BSBUSY-00, BSDVLD-00, and BSDVLD-00 in the explanation of FIG.
Corresponds to BSACEP-00 signal.

In addition, the two bus signals BSSTSA-00 and BSSTSB-00 connected to bus receivers 7 and 8 are
This is a 2-bit response status signal sent from the transfer data receiving device in synchronization with the BSACEP-00 signal. These BSSTSA-00 and
The logical value combination with BSSTSB−00 is (00)
(i.e., if the response is in the second mode),
Indicates that the other device that received this transfer data in input transfer will send the requested data by split transfer (i.e., transfer in the second mode), and if (01) (i.e., transfer in the first mode). If it is a response), this indicates that the other party's device is sending the data using interlock transfer (ie, first mode transfer).

Note that the correspondence between the positive and negative signs + and - in the signal names and the logical values "1" and "0" and the voltage levels H and L is as described above. Also, for example
BSBUSY-00 passes through bus receiver 4
BSBUSY+10, but the 10 in the signal name indicates that it passed through one gate.

When the data processing device shown in FIG. 4 performs transfer with another data processing device, it issues a bus use request. The prioritization mechanism that controls bus contention is as previously described and grants use of the bus to the only data processing device connected to the bus. When this data processing device obtains the right to use the bus, the set signal SETBSY- of the D type flip-flop (hereinafter abbreviated as F/F) 9 shown in FIG.
00 signal becomes logical value “0”. By this F/
F9 is set and the MYBUSY+00 signal is output. Further, the bus driver 1 outputs a BSBUSY-00 signal indicating bus occupancy. This pattern is shown in Figures 5 and 6.

The MYBUSY+00 signal is connected to the input of NAND gate 15. In NAND gate 15,
The above-mentioned MYBUSY+00 signal, USERRQ+00 signal, and BSDVLB-00 signal are input.
USERRQ+00 signal is bus transfer request F/F23
When this data processing device is generating a bus transfer request, the output is a logical value "1". Also,
The BSDVLB-00 signal is the output signal of the NOR gate 18 to which the BSDVLD+10 signal output from the bus receiver 5 and the output of the delay circuit 19 that delays the BSDVLD+10 signal are input. this
The BSDVLB-00 signal has a logical value of "1" (ie, H level) at the stage when MYDVLD+00 is not set. Therefore, the output signal SETVLD-00 of the NAND gate 15 has a logical value of "0" and the D type F/F 10 is set. As a result, the MYDVLD+00 signal becomes the logical value "1",
Bus signal BSDVLD− by bus driver 2
00 becomes a logical value "0" and transfer of the request begins. This pattern is shown in FIGS. 5 and 6.

The other party's device that received the request sends an acknowledgment signal BSACEP-00 in response to the request.
The BSACEP-00 signal is received by the bus receiver 6, becomes the BSACEP+10 signal, becomes the MYDVLR-00 signal, which is input to the NOR gate 16, and resets the F/F 10. (The other input MSTCLR+ of the NOR gate is the master clear signal, which resets the F/F 10 when the power is turned on.) At this time, as the MYDVLD+00 signal disappears, the BSDVLD-00 signal also returns to the logical value "1". .
This pattern is shown in Figures 5 and 6.
, is indicated by .

The other party's device sends the aforementioned response status signal in synchronization with the acknowledgment signal BSACEP-00.
Does it transfer the data requested by interlock transfer by BSSTSA-00 and BSSTSB-00?
It will notify you whether it will be transferred using split transfer. The response status signal is decoded by the decoder 13, and if the request data is transferred by split transfer, the BSSACK+10 signal will have a logic value of "1", and if the request data is transferred by interclock transfer, the BSIACK+10 signal will have a logic value of "1". 1”.

The operation of releasing the bus occupancy when it is notified that requested data will be sent by split transfer will be explained. Can input NAND gate 24
WRITRQ+00 signal has logical value “1” during output transfer
is set to Therefore, since input transfer is currently being performed, this WRITRQ+00 signal has a logical value of "0", and the NAND gate 24
Its output signal regardless of the BSACEP+10 signal
WRTACK-00 is logic value “1” (voltage level H
(corresponds to High). D type F/F2
The BSIACK+10 signal, which is the D input of No. 2, has a logical value of "1" when the other party's device notifies that it will perform interlock transfer as described above at the output of the decoder 13. Since it is now notifying that split transfer will be performed, this signal has a logical value of "0" and is the output signal of the D type F/F22.
INTLOK+00 has a logical value of “0”, so
The output signal INTLAK-00 of the NAND gate 21 is a logical value "1" regardless of the MYACEP+00 signal.
(voltage level H).

When request data is sent by split transfer, the BSSACK+10 signal whose logic value is “1” is
input to NAND gate 20 (NAND gate 2
The other input WRITRQ-00 of 0 has a logical value of "1" during input transfer. ) After being reversed,
The signal becomes the MYBSYR-00 signal by the AND gate 14, and becomes the clock signal of the D type F/F9.
XG00 indicates connected to ground.
Therefore, D type F/F9 is reset at the trailing edge of the MYBSYR-00 signal. For this reason, MYBUSY+
Bus occupancy indication signal due to disappearance of 00 signal
BSBUSY-00 returns to the logical value "1" and releases the bus from occupation. This pattern is shown in Figure 5.
, as shown in .

This completes the input transfer request and waits for the request data to be transferred from the other party's device. When the other device is ready to transfer the requested data, it issues a bus use request, and when the right to use the bus is granted by the priority determination mechanism, it sets the bus occupancy display signal BSBUSY-00 to a logical value of "0". west,
Next, transfer display signal BSDVLD-00 is set to logical value “0”
The requested data will be transferred. If the own device is a receiving device according to the device designation signal (address or channel number) carried on the bus address signal, the D input signal of F/F 11
MYCHAN+00 becomes logical value “1”. As a result, the F/F 11 outputs the signal DVLDDL+00, which is the BSDVLD-00 signal delayed by the delay circuit 17.
is used as the clock and outputs the MYACEP+00 signal. This signal is output to the bus as a BSACEP-00 signal, notifying the other device that the transfer has been received. This transfer completes the data reception.
Since the other device should release the exclusive right to the bus, the encoder 25 encodes the response status signal to indicate split transfer and notifies the other device. Transfer display signal BSDVLD-00 has logical value “1”
Then, the output signal BSDDLY+00 of the delay circuit 19 which inputs the BSDVLD+10 signal causes NOR
The output signal BSDVLB-00 of the gate 18 returns to the logical value "1". Therefore, the output of inverter 12
BSDVLB+10 becomes logical value “0” and F/F1
1 is reset. With this, MYACEP+
00 signal becomes logical value “0” and acknowledge signal
BSACED-00 returns to the logical value "1" and ends the data reception and transfer. This acknowledgment signal
At the trailing edge of BSACEP-00, the other device returns the bus occupancy display signal BSBUSY-00 to the logical value "1" and releases the bus occupancy. This pattern is shown in ~ in Figure 5.

From the above explanation, it is clear that the data processing device of the present invention can perform split transfer.

The case where a response status of interlock transfer is received from the other party's device during input request transfer will be explained with reference to FIGS. 4 and 6.

If the other device returns an interlock transfer response status (see Figure 6) during input request transfer, the output of the decoder 13 in Figure 4
BSIACK+10 becomes logical value “1”. this
BSIACK+10 is the D input of the D type F/F22. At this time, this F/F 22 receives the BSACEP-00 signal from the other device through a delay circuit 28.
A clock is input by ACPDLY+00, which is a signal delayed by , and the INTLOK+00 signal of F/F 22 indicating interlock transfer is set. AND gate 29 and D type F/F30 are
F/F2 with response status signal generated by own device
This is to prevent 2 from being set. This pattern is shown by , in Figure 6.

Since it has now been notified that interlock transfer will be performed, the output of decoder 13 is BSSACK+
10 is logical value “0”, BSIACK+10 is logical value “1”
It is. Therefore, the input of the NAND gate 20, BSSACK+10, has a logical value of "0" and the output of the NAND gate 20 does not change.

Also, since this device is currently driving the BSDVLD-00 signal to transfer an input request to the other device, the MYCHAN indicating that the device has been addressed is also
The +00 signal has a logic value of "0", and MYACEP+00, which is the output of the F/F 11, is never set to a logic value of "1". Therefore, NAND gate 21
The output INTLAK−00 does not change.

WRITRQ+00 which is the input of NAND gate 24
is a signal whose logical value becomes "1" when performing output transfer. Since we are currently performing input transfer,
WRITRQ+00 is a logical value “0” and is a NAND
BSACEP+, the other input of gate 24
10 Its output does not change regardless of changes in the signal.

Therefore, the clock signal MYBSYR- of F/F9
00 is not output, MYBSY+00 is logical value “1”
remains retained. Therefore, BSBSY-00 also holds the logical value "0", continues to occupy the bus, and in this state waits for the requested data to be transferred from the other device.

When the destination device completes preparations for transferring the requested data, unlike split transfer, it does not issue a bus use request, but sends a transfer indication signal BSDVLD-.
The requested data will be transferred along with the 00 signal.
The device designation signal (address or channel number) is
Since it is sent in the same way as split transfer, the D input signal MYCHAN+00 of D type F/F11 is
The logical value becomes "1". The delayed signal of BSDVLD-00 is input to the clock of this D type F/F 11, and the MYACEP+00 signal is set. This signal is passed through bus driver 3 to BSACEP-
00 signal and is returned to the other party's device. The response status signal at this time is a split transfer status since there is no longer a need for transfer. This pattern is shown by ~ in Figure 6.
(The handshake relationship between the BSDVLD-00 and BSACEP-00 signals is the same for both split and interlock transfers.) The MYACEP+00 signal is input to the NAND gate 21, and the other inputs of the gate 21 are
Since the INTLOK+00 signal is input,
The output INTLAK-00 signal of the NAND gate 21 has a logical value of "0". This makes AND gate 1
The output signal MYBSYR-00 of No. 4 has a logic value of "0" and the F/F 9 is reset at the trailing edge of the MYBSYR-00 signal. As a result, the MYBUSY+00 signal returns to the logical value "0", so the bus occupancy display signal
BSBUSY-00 becomes a logical value "1" and releases the bus occupancy state. At the same time, the MYBUSY+00 signal
The INTLOK+00 signal is also returned to the logical value "0". This pattern is shown in ~ in Figure 6.

As is clear from the above explanation, when this data processing device transfers input, either interlock or split transfer is possible depending on the response from the other device when transferring the input request.

Finally, bus occupancy display signal during output transfer
This section explains how to release BSBUSY-00. In the case of output transfer, the requesting device recognizes that it is an output transfer regardless of the response from the other device, so WRITRQ+00, which indicates output transfer, has a logical value of "1", so it can be transferred by inputting the BSACEP+10 signal. NAND
The output WRTACK-00 signal of the gate 24 has a logical value of "0". As a result, the output signal MYBSYR-00 of the AND gate 14 becomes the logical value "0",
F/F9 is reset and the BSBUSY-00 signal returns to the logical value "1".

According to the present invention, the requesting device identifies whether the transfer is interlock transfer or split transfer based on the response of the other device at the time of an input request in input transfer.
A data transfer system is obtained that allows interlock and split transfer to coexist on the same bus, and improves the efficiency of data transfer.

Note that in the present invention, the requesting device does not respond to an instruction regarding the timing of relinquishing the bus exclusive right, but the requesting device does so on the other party's side. In order to abandon the request, the requesting device must perform either the first mode of data transfer (interlock transfer) or the second mode of data transfer (split transfer) for all devices connected to the bus. This is because a means for storing the information to be performed is required, which increases the cost of the device and also results in a lack of flexibility when connecting a new device to the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating a data processing system configured with a single common bus. 101...Single common bus, 102...Central processing unit, 103...I/O control device, 104...Storage device. FIGS. 2 and 3 are time charts illustrating the split transfer method and the interlock transfer method. FIG. 4 is a circuit diagram of a portion of a bus interface in a data processing device according to the present invention. 1, 2, 3, 26, 27... bus driver with inverter function, 4, 5, 6, 7, 8...
Bus receiver with inverter function, 9,1
0,11...D type flip flop, 1
2...Inverter, 13...Decoder, 14...
AND gate, 15...NAND gate, 16...
NOR gate, 17...Delay circuit, 18...NOR
Gate, 19...Delay circuit, 20...NAND gate, 21...NAND gate, 22...D type flip-flop, 23...D type flip-flop, 24...NAND gate, 25
... Encoder, 28 ... Delay circuit, 29 ...
AND gate, 30...D type flip flop. 5 and 6 are time charts of the input transfer method according to the present invention, where FIG. 5 shows the split transfer method and FIG. 6 shows the interlock transfer method.

Claims (1)

[Claims] 1 A device comprising a plurality of data processing devices connected in parallel to a single common bus, wherein a first data processing device among the plurality of data processing devices is connected to another first data processing device among the plurality of data processing devices. In the data transfer method in which a data request is made to a second data processing device and the requested data is transferred, the second data processing device performs the second data processing in response to the data request from the first data processing device. If the device is a device that takes a short time from receiving a data request from the first data processing device to sending back the requested data, the first mode response may be sent in a relatively long time. performs a second mode response, and if the first mode response is performed, the first data processing device does not occupy the bus even after receiving the first mode response. If the second data processing device continues to hold the exclusive right to the bus and relinquishes the exclusive right to the bus when the second data processing device receives the transferred request data, and the second mode response is performed, the second data processing device When the first data processing device receives the response of the second mode, it relinquishes the exclusive right to the bus, and the second data processing device newly secures the exclusive right to the bus, and the first data processing device A data transfer method characterized by transferring requested data to a data processing device.