JPH04299575A - Forming method of polycrystalline semiconductor layer and manufacture of photovoltaic device using the same - Google Patents

Forming method of polycrystalline semiconductor layer and manufacture of photovoltaic device using the same

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Publication number
JPH04299575A
JPH04299575A JP3089927A JP8992791A JPH04299575A JP H04299575 A JPH04299575 A JP H04299575A JP 3089927 A JP3089927 A JP 3089927A JP 8992791 A JP8992791 A JP 8992791A JP H04299575 A JPH04299575 A JP H04299575A
Authority
JP
Japan
Prior art keywords
semiconductor layer
light
polycrystalline semiconductor
photovoltaic device
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3089927A
Other languages
Japanese (ja)
Other versions
JP2702304B2 (en
Inventor
Makoto Tanaka
誠 田中
Kenichiro Wakizaka
健一郎 脇坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP3089927A priority Critical patent/JP2702304B2/en
Publication of JPH04299575A publication Critical patent/JPH04299575A/en
Application granted granted Critical
Publication of JP2702304B2 publication Critical patent/JP2702304B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

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  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To easily form a polycrystalline semiconductor layer at a low temperature, and obtain a method for forming fine unevenness for texture effect on the polycrystalline semiconductor layer. CONSTITUTION:After an amorphous semiconductor layer 2 is formed on a substrate 1, said layer is irradiated with a light 15 via a photo mask 10. In the state that a temperature distribution is formed on the surface, the semiconductor layer 2 is heat-treated and crystallized, thereby forming a polycrystalline semiconductor layer on the surface of which unevenness is formed.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、太陽電池、光センサ等
として用いて好適な多結晶半導体層の形成方法及びこの
多結晶半導体層を用いた光起電力装置の製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a polycrystalline semiconductor layer suitable for use as a solar cell, an optical sensor, etc., and a method for manufacturing a photovoltaic device using this polycrystalline semiconductor layer.

【0002】0002

【従来の技術】一般に、光起電力装置は、ガラス等の透
光性基板上に透明電極と、導電型が夫々p型、i(真性
)型、n型の3層の非晶質半導体層と、裏面電極と、を
この順序に積層して構成されている。
[Prior Art] Generally, a photovoltaic device includes a transparent electrode and three amorphous semiconductor layers of p-type, i (intrinsic) type, and n-type conductivity on a transparent substrate such as glass. and a back electrode are laminated in this order.

【0003】このような光起電力装置は、安価である利
点を有する反面、結晶系シリコンを用いた光起電力装置
と比較して光電変換効率が低いという問題があった。
Although such photovoltaic devices have the advantage of being inexpensive, they have the problem of lower photoelectric conversion efficiency than photovoltaic devices using crystalline silicon.

【0004】また、非晶質半導体層を用いた光起電力装
置は300〜800nmの光感度を有するが、それ以上
の長波長側にも感度を有する光起電力装置が要求される
ようになってきた。
Furthermore, although photovoltaic devices using an amorphous semiconductor layer have photosensitivity in the range of 300 to 800 nm, there is now a demand for photovoltaic devices that are sensitive to longer wavelengths. It's here.

【0005】このため、結晶系の多結晶シリコンを用い
た光起電力装置が注目されている。多結晶シリコンは非
晶質シリコンに比べて移動度が1〜2桁程度高く、また
熱的に安定しており信頼性が高いという特性を有する。 しかも光感度も300〜1100nmと広い。
For this reason, photovoltaic devices using crystalline polycrystalline silicon are attracting attention. Polycrystalline silicon has a mobility that is about one to two orders of magnitude higher than that of amorphous silicon, and is thermally stable and highly reliable. Moreover, the photosensitivity is wide, ranging from 300 to 1100 nm.

【0006】一方、非晶質半導体層を用いた光起電力装
置においては、光電変換効率の改良の一手法として、微
細な凹凸を設けることにより、光半導体層に入射した光
を散乱させて反射損失を減少せしめると共に、光半導体
層中の光路長を増大させて光の吸収効率を高める所謂テ
クスチャ効果を備えたものがある。
On the other hand, in a photovoltaic device using an amorphous semiconductor layer, one method for improving photoelectric conversion efficiency is to provide fine irregularities to scatter and reflect light incident on the optical semiconductor layer. Some materials have a so-called texture effect that reduces loss and increases the optical path length in the optical semiconductor layer to increase light absorption efficiency.

【0007】[0007]

【発明が解決しようとする課題】ところで、従来、多結
晶シリコンは、SILSO多結晶シリコン基板や、キャ
スト多結晶シリコン基板が用いられるが、これら基板は
、基板の形成工程において、1000℃を越える高温で
の熱処理プロセス等、煩瑣で難しい工程が必要であった
。
[Problems to be Solved by the Invention] Conventionally, SILSO polycrystalline silicon substrates and cast polycrystalline silicon substrates have been used for polycrystalline silicon, but these substrates have been exposed to high temperatures exceeding 1000°C during the substrate formation process. This required complicated and difficult steps, such as a heat treatment process.

【0008】そこで、この発明は、多結晶シリコン等の
多結晶半導体層を低温で容易に形成できると共に、テク
スチャ効果のための微細な凹凸を多結晶半導体層に形成
する方法を提供することをその課題とする。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for easily forming a polycrystalline semiconductor layer such as polycrystalline silicon at a low temperature, and also for forming fine irregularities in the polycrystalline semiconductor layer for a texture effect. Take it as a challenge.

【0009】[0009]

【課題を解決するための手段】この発明による多結晶半
導体層の形成方法は、基板上に、非晶質半導体層を形成
した後、この半導体層に選択的に光を照射しつつ、表面
に温度分布を設けた状態で熱処理を施して、前記半導体
層を結晶化させ、表面に凹凸が形成された多結晶半導体
層を形成することを特徴とする。
[Means for Solving the Problems] A method for forming a polycrystalline semiconductor layer according to the present invention includes forming an amorphous semiconductor layer on a substrate, and then selectively irradiating the semiconductor layer with light while The method is characterized in that the semiconductor layer is crystallized by performing heat treatment with a temperature distribution provided, thereby forming a polycrystalline semiconductor layer having an uneven surface.

【0010】この発明による光起電力装置の製造方法は
、基板上に、一導電型の非晶質半導体層を形成する工程
、この半導体層に選択的に光を照射しつつ、表面に温度
分布を設けた状態で熱処理を施して、前記半導体層を結
晶化させ、表面に凹凸が形成された一導電型多結晶半導
体層を形成する工程、この一導電型多結晶半導体層上に
他導電型半導体層を形成する工程、とを備えたことを特
徴とする。
The method for manufacturing a photovoltaic device according to the present invention includes a step of forming an amorphous semiconductor layer of one conductivity type on a substrate, and selectively irradiating this semiconductor layer with light to create a temperature distribution on the surface. a step of crystallizing the semiconductor layer by performing heat treatment in a state in which a polycrystalline semiconductor layer of one conductivity type is formed with unevenness formed on the surface; The method is characterized by comprising a step of forming a semiconductor layer.

【0011】[0011]

【作用】半導体表面において、光照射がされている部分
と、光照射がない部分では温度差が発生する。この温度
分布に応じて、表面に微細な凹凸ができた多結晶半導体
層が形成できる。
[Operation] On the surface of a semiconductor, a temperature difference occurs between a portion that is irradiated with light and a portion that is not irradiated with light. Depending on this temperature distribution, a polycrystalline semiconductor layer with fine irregularities on the surface can be formed.

【0012】0012

【実施例】まず、図1ないし図3に従いこの発明の第1
の実施例について説明する。
[Example] First, according to FIGS. 1 to 3, the first embodiment of the present invention will be described.
An example will be described.

【0013】図1ないし図3は、この発明の多結晶半導
体の形成方法及び光起電力装置の製造方法を示し、図1
は熱処理を施す状態を示す断面図、図2は熱処理を施し
た後の要部拡大断面図、図3は光起電力装置の断面図を
夫々示す。
1 to 3 show a method for forming a polycrystalline semiconductor and a method for manufacturing a photovoltaic device according to the present invention.
2 is an enlarged sectional view of the main part after the heat treatment, and FIG. 3 is a sectional view of the photovoltaic device.

【0014】この実施例においては、まずチタン(Ti
)などからなる金属基板1上にn型不純物として燐(P
)がドープされた膜厚10μmのn型非晶質シリコン層
2を形成する。
In this example, titanium (Ti
) as an n-type impurity on a metal substrate 1 consisting of
) is doped with n-type amorphous silicon layer 2 having a thickness of 10 μm.

【0015】上述のn型非晶質シリコン層2は、例えば
高周波(RF)グロー放電法により、基板1上に形成さ
れる。この時の成膜条件は、シランガス(SiH4)1
0sccm、0.1%の水素(H2)で希釈したホスフ
ィン(PH3)1sccm、基板温度500℃、圧力0
.12Torr、RFパワー20W、成膜速度3Å/秒
である。
The above-mentioned n-type amorphous silicon layer 2 is formed on the substrate 1 by, for example, a radio frequency (RF) glow discharge method. The film forming conditions at this time were silane gas (SiH4) 1
0 sccm, phosphine (PH3) diluted with 0.1% hydrogen (H2) 1 sccm, substrate temperature 500°C, pressure 0
.. The temperature was 12 Torr, the RF power was 20 W, and the deposition rate was 3 Å/sec.

【0016】続いて、図1に示すように、基板1を真空
容器内のヒータ21が内蔵された載置台20に設置する
。そして、光透過部分11と光遮蔽部分12を交互に設
けた石英性のフォトマスク10をn型非晶質シリコン層
2上に設置する。この実施例の光透過部分11と光遮蔽
部分12の幅は約3μm程度である。
Subsequently, as shown in FIG. 1, the substrate 1 is placed in a vacuum container on a mounting table 20 having a built-in heater 21. Then, a quartz photomask 10 having light transmitting portions 11 and light shielding portions 12 alternately provided is placed on the n-type amorphous silicon layer 2 . The width of the light transmitting portion 11 and the light shielding portion 12 in this embodiment is approximately 3 μm.

【0017】その後、真空容器内を排気して真空状態に
保ち、フォトマスク10の上方から可視光又は紫外光1
5を照射し、温度600℃で10時間熱処理を施す。
Thereafter, the inside of the vacuum container is evacuated to maintain a vacuum state, and visible light or ultraviolet light 1 is applied from above the photomask 10.
5 and heat-treated at a temperature of 600° C. for 10 hours.

【0018】この可視光又は紫外光15の照射により、
n型非晶質シリコン層2の表面近傍では、フォトマスク
10の光透過部分11から光が照射された部分は、温度
が620℃と上昇し、光遮蔽部分12により光が照射さ
れない部分は、温度が600℃程度である。
By irradiating this visible light or ultraviolet light 15,
In the vicinity of the surface of the n-type amorphous silicon layer 2, the temperature of the portion irradiated with light from the light-transmitting portion 11 of the photomask 10 rises to 620° C., and the temperature of the portion that is not irradiated with light due to the light-shielding portion 12 increases. The temperature is about 600°C.

【0019】また、基板1近傍のn型非晶質シリコン層
2の温度は基板1の影響で光照射部分と光非照射部分と
の温度差はほとんどない。
Further, the temperature of the n-type amorphous silicon layer 2 near the substrate 1 is influenced by the substrate 1, so that there is almost no difference in temperature between the light irradiated part and the non-light irradiated part.

【0020】この熱処理により、非晶質シリコン層を結
晶化させて、多結晶シリコン層をなすいわゆる固相成長
が行なわれる。この固相成長の結果、n型多結晶シリコ
ン層2aの表面は温度分布の周期に対応した凹凸が形成
される。即ち、図2に示すように、この実施例では6μ
m程度の周期で、凹凸が形成される。この時の凹凸の高
さは2μm程度である。
By this heat treatment, the amorphous silicon layer is crystallized to form a polycrystalline silicon layer through so-called solid phase growth. As a result of this solid phase growth, the surface of the n-type polycrystalline silicon layer 2a is formed with irregularities corresponding to the period of the temperature distribution. That is, as shown in FIG.
The unevenness is formed at a period of about m. The height of the unevenness at this time is about 2 μm.

【0021】然る後、n型多結晶シリコン層2a上に、
p型不純物としてボロン(B)がドープされた膜厚10
0Åのp型非晶質シリコン層3が形成される。
After that, on the n-type polycrystalline silicon layer 2a,
Film thickness 10 doped with boron (B) as p-type impurity
A p-type amorphous silicon layer 3 of 0 Å is formed.

【0022】上述のp型非晶質シリコン層3は、例えば
高周波(RF)グロー放電法により、基板1上に形成さ
れる。この時の成膜条件は、シランガス(SiH4)5
sccm、1%の水素(H2)で希釈したジボラン(B
2H6)25sccm、基板温度120℃、圧力0.2
Torr、RFパワー6Wである。
The above-described p-type amorphous silicon layer 3 is formed on the substrate 1 by, for example, a radio frequency (RF) glow discharge method. The film forming conditions at this time were silane gas (SiH4) 5
sccm, diborane (B) diluted with 1% hydrogen (H2)
2H6) 25sccm, substrate temperature 120℃, pressure 0.2
Torr, RF power 6W.

【0023】そして、図3に示すように、このp型非晶
質シリコン層3上にITOなどの透明電極4をスパッタ
リング法などにより設けて、光起電力装置を得る。
Then, as shown in FIG. 3, a transparent electrode 4 made of ITO or the like is provided on the p-type amorphous silicon layer 3 by sputtering or the like to obtain a photovoltaic device.

【0024】さて、図3に示す薄膜多結晶シリコンを用
いた光起電力装置の光感度を測定したところ、波長80
0nm以上の長波長感度及び波長500nm以下の短波
長感度の何れも向上した。
Now, when we measured the photosensitivity of the photovoltaic device using thin film polycrystalline silicon shown in FIG.
Both the long wavelength sensitivity of 0 nm or more and the short wavelength sensitivity of 500 nm or less were improved.

【0025】次に、図4ないし図6に従いこの発明の第
2の実施例について説明する。
Next, a second embodiment of the present invention will be described with reference to FIGS. 4 to 6.

【0026】図4ないし図6は、この発明の第2の実施
例の多結晶半導体の形成方法及び光起電力装置の製造方
法を示し、図4は熱処理を施す状態を示す断面図、図5
は熱処理を施した後の要部拡大断面図、図6は光起電力
装置の断面図を夫々示す。
4 to 6 show a method for forming a polycrystalline semiconductor and a method for manufacturing a photovoltaic device according to a second embodiment of the present invention, FIG. 4 is a cross-sectional view showing a state in which heat treatment is performed, and FIG.
6 shows an enlarged sectional view of the main part after heat treatment, and FIG. 6 shows a sectional view of the photovoltaic device.

【0027】この実施例においては、n型多結晶シリコ
ン基板5上にp型不純物としてボロン(B)がドープさ
れた膜厚4000Åのp型非晶質シリコン層6を形成す
る。
In this embodiment, a p-type amorphous silicon layer 6 doped with boron (B) as a p-type impurity and having a thickness of 4000 Å is formed on an n-type polycrystalline silicon substrate 5.

【0028】上述のp型非晶質シリコン層6は、例えば
高周波(RF)グロー放電法により、形成される。この
時の成膜条件は、シランガス(SiH4)10sccm
、1%の水素(H2)で希釈したジボラン(B2H6)
5sccm、H230sccm、基板温度350℃、圧
力0.07Torr、RFパワー30Wである。
The above-mentioned p-type amorphous silicon layer 6 is formed by, for example, a radio frequency (RF) glow discharge method. The film forming conditions at this time were 10 sccm of silane gas (SiH4).
, diborane (B2H6) diluted with 1% hydrogen (H2)
5 sccm, H230 sccm, substrate temperature 350° C., pressure 0.07 Torr, and RF power 30 W.

【0029】続いて、図4に示すように、n型多結晶シ
リコン基板5を真空容器内のヒータ21が内蔵された載
置台20に設置する。そして、前述と同様に光透過部分
11と光遮蔽部分12を交互に設けた石英性のフォトマ
スク10をp型非晶質シリコン層6上に設置する。この
実施例の光透過部分11と光遮蔽部分12の幅は約0.
5μm程度である。
Subsequently, as shown in FIG. 4, the n-type polycrystalline silicon substrate 5 is placed on a mounting table 20 containing a heater 21 in a vacuum container. Then, as described above, a quartz photomask 10 having light transmitting portions 11 and light shielding portions 12 alternately provided is placed on the p-type amorphous silicon layer 6. The width of the light transmitting portion 11 and the light shielding portion 12 in this embodiment is approximately 0.
It is about 5 μm.

【0030】その後、真空容器内を排気して真空状態に
保ち、フォトマスク10の上方から可視光又は紫外光を
照射し、温度650℃で10時間熱処理を施す。
Thereafter, the inside of the vacuum container is evacuated to maintain a vacuum state, visible light or ultraviolet light is irradiated from above the photomask 10, and heat treatment is performed at a temperature of 650° C. for 10 hours.

【0031】この可視光又は紫外光を照射により、前述
と同様にp型非晶質シリコン層6の表面近傍では、光が
照射された部分は、温度が670℃と上昇し、光が照射
されない部分は、温度が650℃程度である。
By irradiating this visible light or ultraviolet light, in the vicinity of the surface of the p-type amorphous silicon layer 6, the temperature rises to 670° C. in the irradiated portion, and the light is not irradiated. The temperature of the portion is approximately 650°C.

【0032】また、n型多結晶シリコン基板5近傍のp
型非晶質シリコン層6の温度は基板1の影響で光照射部
分と光非照射部分との温度差はほとんどない。
In addition, p near the n-type polycrystalline silicon substrate 5
Due to the influence of the substrate 1, there is almost no temperature difference in the temperature of the mold amorphous silicon layer 6 between the light irradiated area and the non-light irradiated area.

【0033】この熱処理による固相成長の結果、p型多
結晶シリコン層6aの表面は温度分布の周期に対応した
凹凸が形成される。即ち、図5に示すように、この実施
例では1μm程度の周期で、凹凸が形成される。この時
の凹凸の高さは2000Å程度である。
As a result of the solid-phase growth caused by this heat treatment, the surface of the p-type polycrystalline silicon layer 6a has irregularities corresponding to the period of the temperature distribution. That is, as shown in FIG. 5, in this example, unevenness is formed at a period of about 1 μm. The height of the unevenness at this time is about 2000 Å.

【0034】然る後、図6に示すように、p型多結晶シ
リコン層6a上に、アルミニウム(Al)を蒸着などに
より形成し、このAlをパターニングして櫛型電極7を
形成して光起電力装置を得る。
Thereafter, as shown in FIG. 6, aluminum (Al) is formed on the p-type polycrystalline silicon layer 6a by vapor deposition or the like, and this Al is patterned to form a comb-shaped electrode 7, which is used for light emission. Obtain an electromotive force device.

【0035】さて、図6に示す薄膜多結晶シリコンを用
いた光起電力装置の光感度を測定したところ、波長80
0nm以上の長波長感度及び波長500nm以下の短波
長感度の何れも向上した。
Now, when we measured the photosensitivity of the photovoltaic device using thin film polycrystalline silicon shown in FIG.
Both the long wavelength sensitivity of 0 nm or more and the short wavelength sensitivity of 500 nm or less were improved.

【0036】〔発明の効果〕以上説明したように、本発
明によれば、半導体表面において、光照射部分と光非照
射部分との間で温度差が発生し、この温度分布に応じて
、表面に微細な凹凸ができた多結晶半導体層を形成する
ことができる。従って、この多結晶半導体層を光起電力
装置に用いると所謂テクスチャ効果により、光電変換効
率が向上する。
[Effects of the Invention] As explained above, according to the present invention, a temperature difference occurs between the light irradiated part and the non-light irradiated part on the semiconductor surface, and the surface temperature changes according to this temperature distribution. A polycrystalline semiconductor layer having fine irregularities can be formed. Therefore, when this polycrystalline semiconductor layer is used in a photovoltaic device, the photoelectric conversion efficiency is improved due to the so-called texture effect.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】  この発明の第1の実施例を示し、熱処理を
施す状態を示す断面図である。
FIG. 1 is a sectional view showing a first embodiment of the present invention and showing a state in which heat treatment is performed.

【図2】  この発明の第1の実施例を示し、熱処理を
施した後の要部拡大断面図である。
FIG. 2 is an enlarged cross-sectional view of the main part after heat treatment, showing the first embodiment of the present invention.

【図3】  この発明の第1の実施例を示し、光起電力
装置の断面図である。
FIG. 3 is a sectional view of a photovoltaic device, showing a first embodiment of the present invention.

【図4】  この発明の第2の実施例を示し、熱処理を
施す状態を示す断面図である。
FIG. 4 is a sectional view showing a second embodiment of the present invention and showing a state in which heat treatment is performed.

【図5】  この発明の第2の実施例を示し、熱処理を
施した後の要部拡大断面図である
FIG. 5 is an enlarged sectional view of the main part after heat treatment, showing a second embodiment of the present invention.

【図6】  この発明の第2の実施例を示し、光起電力
装置の断面図である。
FIG. 6 shows a second embodiment of the invention and is a sectional view of a photovoltaic device.

【符号の説明】 1  基板 2  n型非晶質シリコン 2a  n型多結晶シリコン 3  p型非晶質シリコン 4  透明電極 10  フォトマスク 5  n型多結晶シリコン基板 6  p型非晶質シリコン 6a  p型多結晶シリコン 7  櫛型電極[Explanation of symbols] 1 Board 2 N-type amorphous silicon 2a N-type polycrystalline silicon 3 P-type amorphous silicon 4 Transparent electrode 10 Photomask 5 N-type polycrystalline silicon substrate 6 p-type amorphous silicon 6a p-type polycrystalline silicon 7 Comb-shaped electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  基板上に、非晶質半導体層を形成した
後、この半導体層に選択的に光を照射しつつ、表面に温
度分布を設けた状態で熱処理を施して、前記半導体層を
結晶化させ、表面に凹凸が形成された多結晶半導体層を
形成することを特徴とする多結晶半導体層の形成方法。
1. After forming an amorphous semiconductor layer on a substrate, heat treatment is performed while selectively irradiating the semiconductor layer with light and creating a temperature distribution on the surface to form the semiconductor layer. A method for forming a polycrystalline semiconductor layer, which comprises crystallizing and forming a polycrystalline semiconductor layer having an uneven surface.
【請求項2】  基板上に、一導電型の非晶質半導体層
を形成する工程、この半導体層に選択的に光を照射しつ
つ、表面に温度分布を設けた状態で熱処理を施して、前
記半導体層を結晶化させ、表面に凹凸が形成された一導
電型多結晶半導体層を形成する工程、この一導電型多結
晶半導体層上に他導電型半導体層を形成する工程、とか
らなる光起電力装置の製造方法。
2. A step of forming an amorphous semiconductor layer of one conductivity type on a substrate, selectively irradiating the semiconductor layer with light and performing heat treatment with a temperature distribution on the surface, A step of crystallizing the semiconductor layer to form a polycrystalline semiconductor layer of one conductivity type with unevenness formed on the surface, and a step of forming a semiconductor layer of another conductivity type on the polycrystalline semiconductor layer of one conductivity type. Method of manufacturing a photovoltaic device.
JP3089927A 1991-03-27 1991-03-27 Method for forming polycrystalline semiconductor layer and method for manufacturing photovoltaic device using the same Expired - Fee Related JP2702304B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3089927A JP2702304B2 (en) 1991-03-27 1991-03-27 Method for forming polycrystalline semiconductor layer and method for manufacturing photovoltaic device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3089927A JP2702304B2 (en) 1991-03-27 1991-03-27 Method for forming polycrystalline semiconductor layer and method for manufacturing photovoltaic device using the same

Publications (2)

Publication Number Publication Date
JPH04299575A true JPH04299575A (en) 1992-10-22
JP2702304B2 JP2702304B2 (en) 1998-01-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2702304B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009224770A (en) * 2008-02-19 2009-10-01 Semiconductor Energy Lab Co Ltd Manufacturing method for photoelectric conversion device
JP2011159872A (en) * 2010-02-02 2011-08-18 Sharp Corp Method of manufacturing electrode, method of manufacturing solar cell, and device of manufacturing photoelectric conversion element

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6154068U (en) * 1984-09-13 1986-04-11
JPS6431162U (en) * 1987-08-13 1989-02-27
JPH0336613Y2 (en) * 1986-08-07 1991-08-02

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6154068U (en) * 1984-09-13 1986-04-11
JPH0336613Y2 (en) * 1986-08-07 1991-08-02
JPS6431162U (en) * 1987-08-13 1989-02-27

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009224770A (en) * 2008-02-19 2009-10-01 Semiconductor Energy Lab Co Ltd Manufacturing method for photoelectric conversion device
JP2011159872A (en) * 2010-02-02 2011-08-18 Sharp Corp Method of manufacturing electrode, method of manufacturing solar cell, and device of manufacturing photoelectric conversion element

Also Published As

Publication number Publication date
JP2702304B2 (en) 1998-01-21

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