JPH04299846A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the reliability of an interconnection layer at the upper layer by forming a flat interlayer insulating film even when an element is made fine. CONSTITUTION:The first of this invention is as follows: e.g. interconnection-layer patterns 12 are formed on a semiconductor substrate 11; a surface having recessed and protruding parts is obtained; after that, an interlayer insulating film 13 is formed by a CVD method; and the film is etched and flattened by an isotropic etching operation in which the gas pressure of an etching gas is lowered to an extent that the mean free path lambda of an active species in the etching gas satisfies the following formula: lambda >= S-2d, where S represents the maximum width of a gap between the interconnection-layer patterns (between the protruding parts) and (d) represents the film thickness of the interlayer insulating film when it is deposited. At this time, it is desirable that the semiconductor substrate 11 is arranged parallel to a gas stream or that the rear of the semiconductor substrate 11 is arranged so as to be faced with the upstream side with reference to the gas stream. The second of this invention is as follows: the first flattening process is by using an isotropic etching operation but by using a directive etching operation from an oblique direction.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to planarization of a semiconductor device having multilayer wiring.

0003

2. Description of the Related Art In recent years, as semiconductor integrated circuits have become more highly integrated and miniaturized, wiring has become more multilayered. However, as elements become finer and wiring becomes more multilayered, a problem arises in that the wiring layer itself becomes disconnected due to differences in level caused by fine elements, interlayer insulating films, and wiring layers. In order to reduce these defects, the etch-back method and the use of SOG (Spin on Glass) as an interlayer insulating film are used to reduce the level difference caused by fine elements, interlayer insulating films, and wiring layers.
Planarization methods using polyimide and polyimide have been developed. However, as elements become finer, the line width and spacing between interconnects are reduced, and the aspect ratio of interconnects is increased to reduce interconnect resistance. When the interlayer insulating film is deposited to such an extent that smooth planarization can be achieved, "holes" are formed in the gaps between the interconnections 32. Further, even when polyimide is applied to the SOG 33, the SOG 33 and the polyimide do not enter into the gaps between the wiring lines 32, and "s" 34 are formed. When "holes" are formed in the gaps between wirings in this way, there is a problem in that the upper wiring layer is broken due to the step difference, and sufficient planarization cannot be achieved.

0004

[Problems to be Solved by the Invention] As described above, it is possible to reduce the spacing between wirings and the gaps between wirings in accordance with the miniaturization of elements.
When wiring with a high aspect ratio is formed, even if an etch-back method or a conventional planarization method using SOG or polyimide as an interlayer insulating film is used, "holes" will be formed in the gaps between the wirings, and the steps will affect the upper layer. There was a problem in that a step break occurred in the wiring layer. The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to form a flat interlayer insulating film even when devices are miniaturized, and to prevent breaks in the upper wiring layer and improve reliability.

[Configuration of the invention]

[0006]

[Means for Solving the Problems] Accordingly, in the first aspect of the present invention, after forming, for example, a wiring layer pattern on a semiconductor substrate to obtain an uneven surface, an interlayer insulating film is formed by a CVD method, and this is etched. Planarization is performed by isotropic etching in which the gas pressure of the etching gas is lowered to such an extent that the mean free path λ of active species in the gas satisfies the following equation.

[0007]λ≧S-2d
(1) S: Maximum width of gap between wiring layer patterns (between protrusions) d: Film thickness of interlayer insulating film during deposition Here, preferably, the semiconductor substrate is arranged parallel to the gas flow, or The semiconductor substrate is arranged so that the back surface faces upstream with respect to the gas flow.

In the second aspect of the present invention, the first planarization step is performed using directional etching from an oblique direction instead of isotropic etching.

[0009]

[Operation] According to the first configuration, etching is performed so that the mean free path λ of the active species of the etching gas is larger than the gap formed between the interlayer insulating films deposited from the side wall of the wiring section. By adjusting the gas pressure of the gas,
Since the interlayer insulating film is etched by isotropic etching while preventing the active species in the etching gas from reaching the insulating film deposited at the bottom of the gap between interconnect layers, the insulating film deposited at the bottom of the gap between interconnect layers is etched. Instead, only the interlayer insulating film deposited directly above the wiring layer and from the sidewall of the wiring portion is etched. As a result, the gap that existed between the wiring layers is widened by etching the upper part of the insulating film, making it possible to reduce the aspect ratio of the gap between the wiring layers, even using conventional planarization technology. The level difference is such that it can be flattened.

Thereafter, if necessary, an interlayer insulating film is deposited again and planarized by a method such as etch-back.

[0011] In this way, a flat interlayer insulating film can be formed, step breakage caused by the step difference in the "s" can be prevented, and highly reliable wiring can be formed.

According to the second configuration, only the interlayer insulating film deposited directly above the wiring layer and from above the side wall of the wiring portion is etched by directional etching from an oblique direction. As a result, as in the first aspect of the present invention, the gap that existed between the wiring layers is widened by etching the upper part of the insulating film, making it possible to reduce the aspect ratio of the gap between the wiring layers. The level difference is such that it can be flattened even with the use of the flattening technique described above.

Thereafter, similarly, if necessary, an interlayer insulating film is deposited again and planarized by a method such as etch-back.

[0014] In this way, a flat interlayer insulating film can be formed without the occurrence of "scratches", and highly reliable wiring can be formed.

[0015]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Example 1 First, as shown in FIG. 1(a), a first wiring pattern 12 made of an aluminum layer with a wiring width of 1 μm and a film thickness of 1 μm is formed on the surface of a silicon substrate 11 on which an element region is formed.
form.

After this, as shown in FIG. 1(b), the CV
Silicon oxide film 1 as a first interlayer insulating film by method D
form 3. At this time, the film thickness A between the first wiring patterns 12 and the film thickness B of the side walls of the first wiring patterns 12 are 600 nm and 420 nm, respectively.

Next, as shown in FIG. 2, this semiconductor substrate 10 is placed in an etching chamber 24 so as to be parallel to the etching gas flow path 15, and the plasma activation generated in the plasma generation chamber 22 is Transport the seeds 25 to the tube 23
is introduced into the etching chamber 24 through the wafer. Here, CF4 with a pressure of about 0.5 Torr was introduced into the chamber as an etching gas, and as shown in FIG.
CDE (CHEMICAL DRY) until m.
Etching is performed using the ETCHING method. At this time, the mean free path λ of F radicals in CF4 turned into plasma
is about λ=10 μm at a gas pressure of 0.5 Torr, so the interconnect spacing S, the thickness d of the insulating film deposited from the interconnect layer in the interconnect gap, and the mean free path λ of the active species in the etching gas The relationship is F radical mean free path λ = 10 μm wiring spacing S = 1
μm Since the film thickness d of the silicon oxide film 13 deposited from the sidewall of the wiring layer in the wiring layer gap is 0.42 μm, the above (
1) Substituting into the formula: 10μm > 1μm -2 x 0.42μm = 0.16
μm, and it can be seen that the above formula (1) is fully satisfied.

In this etching process, the semiconductor substrate was placed in the etching chamber parallel to the etching gas flow path 15, but as shown in FIG. It may be installed perpendicularly to the etching gas flow path so that the back surface is exposed. As shown in FIG. 3, the semiconductor substrate 11 is placed in the etching chamber 24 so as to be perpendicular to the etching gas flow path 26, and the plasma active species 25 generated in the plasma generation chamber 22 are passed through the transport pipe 23. It is introduced into the etching chamber 24. This also prevents the active species of etching from reaching the insulating film accumulated at the bottom of the gap between the first wiring layer patterns.

The silicon oxide film 13 thus deposited between the first wiring patterns 11 is not etched and maintains a film thickness of 600 nm, and the aspect ratio Rp of the gap between the wiring layer patterns is smaller than that of the first layer wiring. Immediately after patterning, Rp = 1, but after etching, Rp =
It is 0.2.

After this, as shown in FIG. 1(d), CVD
A second silicon oxide film 14 having a thickness of 2 μm is deposited as an interlayer insulating film on this upper layer by a method.

Then, as shown in FIG. 1F, a resist (not shown) is coated on the second silicon oxide film 14, planarized, and etched back to form the first wiring layer 11.
Etching is performed until the upper film thickness is approximately 1 μm, and planarization is performed.

[0023] In this way a flat surface can be obtained. Therefore, the second wiring pattern formed on this upper layer can be microfabricated with high precision, and it is possible to obtain a highly reliable multilayer wiring without any step breaks.

[0024] In the above embodiment, normal etch-back was performed after planarization using low-pressure isotropic etching, but it is possible to obtain sufficient flatness by planarization using isotropic etching. If possible, the etch-back process may be omitted.

[0025] Furthermore, this flattening process using low-pressure isotropic etching may be repeated.

Furthermore, it goes without saying that this technique may be applied only to the upper layer of multilayer wiring with a large aspect ratio.

Example 2 Next, a second embodiment of the present invention will be described.

In the above embodiment, planarization was performed by low-pressure isotropic etching, but in this example, directional etching from an oblique direction removed the deposits directly above the wiring layer and from the top of the sidewall of the wiring part. Planarization is performed by selectively etching the interlayer insulating film.

First, as in Example 1, as shown in FIG. 4(a), on the surface of the silicon substrate 11 on which the element region is formed, a wiring made of an aluminum layer with a width of 1 μm and a film thickness of 1 μm is formed.
A first wiring pattern 12 is formed.

After this, as shown in FIG. 4(b), the CV
Silicon oxide film 1 as a first interlayer insulating film by method D
form 3. At this time, the film thickness A between the first wiring patterns 12 and the film thickness B of the side walls of the first wiring patterns 12 are 600 nm and 420 nm, respectively. Here, in order to prevent the wiring pattern from being damaged by anisotropic etching, the film thickness B of the side wall of the first wiring pattern 12 must be half of the film thickness A between the first wiring patterns 12. It is necessary to deposit it so that it becomes the above.

Next, as shown in FIG. 4(c), this semiconductor substrate 11 is placed in an etching chamber, ions are irradiated so that the incident angle to the substrate surface is θ=31°, and ion milling is performed. The silicon oxide film 13 is etched directly above the wiring pattern and on one side of the sidewall. This angle is so that only the insulating film directly above the interconnects is etched due to the shadowing effect between the interconnects and the interlayer insulating film, and the insulating film deposited in the gaps between the interconnects is not etched.

Subsequently, as shown in FIG. 4(d), ions are irradiated so that the incident angle to the substrate surface is θ=-16.7°, and the wiring pattern of the silicon oxide film 13 is formed by ion milling. Etch the surface directly above and the other surface of the sidewall so that the film thickness directly above the wiring pattern is approximately 20 nm. This angle is also used to ensure that only the insulating film directly above the wiring is etched due to the shadowing effect of the wiring and the interlayer insulating film, and the insulating film deposited in the gap between the wirings is not etched.

The silicon oxide film 13 thus deposited between the first wiring patterns 11 is not etched and maintains a film thickness of 600 nm, and the aspect ratio Rp of the gap between the wiring layer patterns is smaller than that of the first layer wiring. Immediately after patterning, Rp = 1, but after etching, Rp =
It is 0.58.

After this, as shown in FIG. 4(e), CVD
A second silicon oxide film 14 having a thickness of 2 μm is deposited as an interlayer insulating film on this upper layer by a method.

Then, as shown in FIG. 4F, a resist (not shown) is applied to the second silicon oxide film 14, planarized, and etched back to form the first wiring layer 11.
Etching is performed until the upper film thickness is approximately 1 μm, and planarization is performed.

[0036] In this way a flat surface can be obtained. Therefore, the second wiring pattern formed on this upper layer can be microfabricated with high precision, and it is possible to obtain a highly reliable multilayer wiring without any step breaks.

In the above embodiment, normal etch-back was performed after planarization using anisotropic etching, but if sufficient flatness can be obtained by planarization using anisotropic etching, , the etch-back process may be omitted.

[0038] Furthermore, this planarization process using anisotropic etching may be repeated.

Furthermore, it goes without saying that this technique may be applied only to the upper layer of multilayer wiring with a large aspect ratio.

Further, in the above embodiment, the ion milling method was used for anisotropic etching, but the present invention is not limited to this, and other anisotropic etching methods such as RIE may be used.

Furthermore, if the distribution of elements on the semiconductor substrate is not uniform and there are parts with dense wiring and parts with sparse wiring, this method may be used only for planarizing the dense parts.

Furthermore, although the formation of the interlayer insulating film on the wiring layer has been described, it may be used for planarization when forming the interlayer insulating film prior to forming the first wiring layer.

Other modifications may be made as appropriate without departing from the scope of the present invention.

[0044]

As explained above, according to the present invention, the mean free path λ of the active species of the etching gas is greater than the gap formed between the interlayer insulating films deposited from the sidewalls of the wiring section. In order to prevent active species in the etching gas from reaching the insulating film deposited at the bottom of the gap between wiring layers, etching is performed using isotropic etching with a low gas pressure of the etching gas. Therefore, the insulating film deposited at the bottom of the gap between wiring layers is not etched, and only the interlayer insulating film deposited directly above the wiring layer and from the side walls of the wiring part is etched. This makes it possible to achieve high level planarization and form highly reliable wiring.

Further, according to the second configuration, only the interlayer insulating film deposited directly above the wiring layer and from the top of the side wall of the wiring part is etched by directional etching from an oblique direction, so that the wiring pattern is By reducing the aspect ratio of the gap, sufficient planarization can be achieved and highly reliable wiring can be formed.

[Brief explanation of drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an etching apparatus used in the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a modification of the etching apparatus used in the manufacturing process of the semiconductor device of the present invention.

FIG. 4 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a conventional etch-back method.

[Explanation of symbols]

11 Silicon substrate 12 First wiring layer pattern 13 Interlayer insulation film 14 Interlayer insulation film 15 Etching gas flow 22 Plasma generation chamber 23 Transport pipe 24 Etching chamber 25 Plasma active species

Claims (2)

[Claims] Claim 1: An interlayer insulating film deposition step in which an interlayer insulating film is deposited on a semiconductor substrate with an uneven surface, and the gas pressure of the etching gas is adjusted to such an extent that the mean free path of active species in the etching gas satisfies the following equation: A method for manufacturing a semiconductor device, comprising a planarization step of etching and planarizing the interlayer insulating film using a low isotropic etching method. λ≧S-2d λ: Mean free path S: Maximum width of gap between convex parts d: Film thickness of interlayer insulating film during deposition 2. A method comprising: an interlayer insulating film deposition step of depositing an interlayer insulating film on the surface of a semiconductor substrate having an uneven surface; and a planarization step of performing directional etching from an oblique direction on the semiconductor substrate. A method for manufacturing a semiconductor device.