JPH04301295A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve access time by making the rising of a SRAM word line steep. CONSTITUTION:Electric discharge circuits 101 and 102 supply the inverse signals 13 and 15 of output signals 12 and 14 in word driver circuits 11a and 11b to capasitative elements C and C11, bipolar transistors Q7 and Q17 are instantaneously turned on and the voltage of the word lines WL1 and WL11 are suddenly descended. The electric discharge circuits shift the word lines from selection to non-selection at high speed without increasing normal power consumption so as to attain the high-speed of access.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a word line discharge circuit for a static semiconductor memory device (hereinafter referred to as SRAM) such as ECL or CML using bipolar transistors.

0002

2. Description of the Related Art In general, in an SRAM, memory cells for one row are connected in parallel between one word line and one hold line, and the memory state of each memory cell, that is, the state of a flip-flop is held. To do this, a hold current flows from the word line through the memory cell to the hold line.

[0003] Such word line selection is performed by raising the word line potential using a word driver. In this case, since the word driver is an emitter follower, the word line changes from a non-selected state to a selected state. The time, ie, the word line rise time, is relatively short. On the other hand, the change time of the word line from the selected state to the non-selected state, that is, the fall time of the word line, depends on the amount of charge accumulated in the parasitic capacitance of the word line and the magnitude of the hold current. This is because the emitter follower transistor is cut off at the falling edge. FIG. 5 shows a voltage waveform on a word line of an SRAM without a discharge circuit, and the voltage drop rate is small immediately after the voltage falls.

By the way, the rise and fall characteristics of word lines in SRAM not only occupy a considerable portion of the memory access time, but also define the operation cycle. Therefore, efforts are being made to improve the falling characteristics without increasing the hold current.

In recent years, in order to speed up the fall of the word line, SRAMs cause a discharge current to flow intensively to a selected word line, as shown in FIG. In addition to this, it is common to install a circuit that flows another discharge current (I103).

However, in this circuit configuration, when the potential of the word line going from selection to non-selection becomes lower than the potential of the word line going from non-selection to selection, the common current source I10
3 switches from the former word line to the latter word line, so as shown in FIG. 6, the potential drop of the unselected word line becomes very slow from the middle of the fall (time t1).

The discharge circuit shown in FIG. 4 improves the drawbacks of the conventional example, and each row of memory cells includes Darlington-connected bipolar transistors Q105 to Q108, capacitors C101 and C102, and resistors R101 to R1.
04, the voltage on the word line is delayed by a time determined by the time constant R×C, and the current path to the current source I106 changes.

Therefore, in the conventional example shown in FIG. 4, the discharge current continues to flow until the word line voltage falls sufficiently. The voltage waveform on the word line in the conventional example shown in FIG. 4 has an improved fall time as shown in FIG.

[0009]

However, even with the SRAM shown in FIG. 4, the falling waveform of the word line is still not satisfactory in recent SRAMs that pursue ultra-high speed performance.

In the delayed discharge circuit shown in FIG.
After the time determined by ×C, the current flowing to the current source I106 is ultimately supplied from the selected word line, so the falling waveform of the word line that transitions to non-selection becomes slack from before reaching the low potential level (time t2). It becomes something. Although this characteristic can be improved by increasing the time constant, if the time constant is made too large, the high potential state of the selected word line will be maintained longer than necessary, making it impossible to move on to the next operation cycle, and causing double selection of memory cells. There was a problem in that situations such as these occurred.

[0011]

[Means for Solving the Problems] The gist of the present invention is to provide a static memory cell connected between a word line, a hold line, a word line and a hold line, and a memory cell connected to the memory cell when the memory cell is not selected. The word line driver unit maintains the word line at a first level and supplies a hold current to hold the stored data bit, and shifts the word line to a second level when selecting a memory cell to permit access. In the semiconductor memory device, the word line driver unit includes a word driver circuit that generates an output signal when selected in response to an address decode signal, and a word driver circuit that generates an output signal at the time of selection in response to an address decode signal, and a word line driver circuit that generates a first word line in response to an output signal of the word driver circuit.
An emitter follower transistor for transitioning from one level to a second level, and a first emitter follower transistor interposed between a word line and a discharge line.
a bipolar transistor and a capacitive element connected to the base of the first bipolar transistor; when an inverted signal of an output signal is supplied to the capacitive element during transition from selection to non-selection, the first bipolar transistor is turned on for a predetermined time;
The present invention also includes a discharge circuit that connects the word line to the discharge line.

0012

When the word line is switched from the selected state to the non-selected state, the discharge circuit connects the word line to the discharge line for a predetermined period of time in response to an inverted signal, and rapidly changes the word line from the second level to the non-selected state. Return to level 1.

[0013]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 1 is a circuit diagram showing the vicinity of a word line drive circuit in a static semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, 10 is an address decoder circuit, and 11a and 11b are word driver circuits. That is, memory cells 30 arranged in multiple rows
Select only one line from 33. For example, when the decoder circuit 10 specifies a row of memory cells 30 and 31, the word driver circuit 11a sets only the output line 12 to a high potential,
The other driver circuits 11b including the output line 14 remain at a low potential.

Therefore, the emitter follower transistor Q6, which receives the high potential output line 12, is connected to the word lines WL1,
Hold line HL1 is designated and word line WL1 is brought to a high potential state. On the other hand, the low potential output line 14 is the word line WL1
1. Keep the hold line HL11 in a non-selected state and put the word line WL11 in a low potential state.

Now, let us consider the operation when the word line WL1 is selected and the word line WL11 is selected.

At the same time as the output line 12 of the driver circuit 11a begins to transition from a high potential to a low potential, the output line 14 of another driver circuit 11b begins to transition from a low potential to a high potential. Therefore, in addition to supplying the previous hold current, the emitter follower transistor Q16 also supplies the word line W
An attempt is made to bring WL11 to a high potential while charging the parasitic capacitance of L11.

On the other hand, the emitter follower transistor Q6 tries to cut off as the base signal decreases, but the parasitic capacitance of the word line WL1 must be discharged.
Hold current alone is not sufficient.

However, in this embodiment, the discharging transistor Q7 assists in discharging the parasitic capacitance. That is, at the same time that the output line 12 of the driver circuit 11a starts to shift to a low potential, the output line 13, which is an inverted signal thereof, shifts to a high potential. As a result, the output line 13 momentarily increases the base potential of the discharge transistor Q7 via the capacitor C1, thereby making the discharge transistor Q7 conductive and forming a discharge path for the parasitic capacitance of the word line WL1 described above. . Therefore, the level of the word line WL1 can be instantaneously changed from a high potential to a low potential, and as shown in FIG. 8, the falling waveform of the word line in this embodiment is extremely sharp. Note that since the transistor Q7 is in a conductive state only for a time determined by the time constant R×C, it does not consume power regularly.

Bipolar transistor Q7 and capacitive element C
1 (or Q17 and C11) is the discharge circuit 101 (102
), and discharge circuits 101 and 102 and word driver circuits 11a and 11b form a word line driver unit 103.
Configure.

FIG. 2 is a circuit diagram showing the vicinity of a word line drive circuit according to a second embodiment of the present invention. In the first embodiment, the discharge circuit is connected only to the word line, but if only the word line suddenly falls during the transition from selection to non-selection and the fall of the hold line is delayed, the memory cell The hold voltage may be compressed and the hold function may be lost. In order to correct this, discharge transistors Q53 and Q56 having the same function as the word line discharge circuit are also installed in the hold lines HL51 and HL52. As a result, both the word line and the hold line fall sharply.

In any of the embodiments, the connection point of the capacitive coupling is an inverted signal terminal different from the word driver drive signal terminal, so the word driver signal itself is not adversely affected by the connection of the capacitor. It never happens.

In the second embodiment, bipolar transistors Q52 and Q53 and capacitive element C50 (and/or bipolar transistors Q55 and Q56 and capacitive element C51)
constitutes a discharge circuit 201.

[0024]

As explained above, the present invention uses an inverted signal of a word driver drive signal to make a capacitively coupled input transistor conductive only when changing from selected to non-selected, thereby improving word line and This has the effect of instantly discharging the charge accumulated in the parasitic capacitance of the hold line, making the fall of the word line and hold line steeper, and greatly contributing to shortening access time and speeding up the operation cycle.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a main part of a static memory circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional word line drive circuit.

FIG. 4 is a circuit diagram of a conventional delayed discharge type word line drive circuit.

FIG. 5 is a waveform diagram of a conventional word line without a discharge circuit.

6 is a waveform diagram of a word line in the conventional example of FIG. 3; FIG.

7 is a waveform diagram of a word line in the conventional example of FIG. 4; FIG.

FIG. 8 is a waveform diagram of word lines in the first embodiment.

[Explanation of symbols]

10, 51 Decoder circuit 11, 52, 53 Word driver logic circuit VR
1 Reference voltage VCS Constant current source reference voltage Q1 to Q10
8 Transistors R1 to R104 Resistors 16, 18, 61, 63, 101, 103, 105, 1
07 Word line 17, 19, 62, 64, 102, 104, 106, 1
08 Hold line 20~23, 65~68 Digit line 30~3
3,70-73 Memory cells I101-I107
Constant current source VEE Current D101 to D102 Diodes 101, 102
, 201 Discharge circuit 103 Word line driver unit

Claims (2)

[Claims] 1. A word line, a hold line, a static memory cell connected between the word line and the hold line, and a word line for holding data bits stored in the memory cell when the memory cell is not selected. A semiconductor memory device comprising a word line driver unit that maintains a word line at a first level and supplies a hold current, and shifts the word line to a second level to permit access when selecting a memory cell, wherein the word line driver The unit includes a word driver circuit that generates an output signal when selected in response to an address decode signal, and an emitter follower transistor that transitions the word line from a first level to a second level in response to the output signal of the word driver circuit. A first bipolar transistor interposed between the word line and the discharge line and a capacitive element connected to the base of the first bipolar transistor, and an inverted signal of the output signal is supplied to the capacitive element when transitioning from selection to non-selection. and a discharge circuit that turns on the first bipolar transistor for a predetermined period of time to connect the word line to the discharge line. 2. The semiconductor memory device according to claim 1, wherein the discharge circuit further includes a second bipolar transistor interposed between the hold line and the discharge line and having a base connected to the capacitive element.