JPH04301B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to floating point arithmetic systems, and in particular to numbers that are expressed in normal floating point numbers and numbers that cannot be displayed using this method and require separate floating point numbers. The present invention relates to a floating-point arithmetic system suitable for efficiently processing a mixture of .

Prior Art Figure 1 is an example of a floating point representation currently used in many data processing devices, where 1 is a 1-bit sign, 2 is an exponent part with a 7-bit 64 remainder code, and 3 is a 56-bit 16 It is a 14-digit mantissa. Floating point representations are usually normalized and used
The most significant 4-bit digit of the mantissa 3 is generally not 0 except in the case of a true 0 in which all bits of the representation are 0. In this state, if the maximum absolute value that can be expressed in the display in Figure 1 is Ω, and the minimum absolute value is ω, then Ω = (1-16 ^-14 ) 16 ⁶³ ω = 16 ^-1・16 ^-64 = 16 ^-65 . Therefore, the absolute value of the calculation result may exceed Ω or be less than ω. When Ω is exceeded, the upper half overflows, and when it is not 0 and less than ω, the lower half overflows. In the case of upper overflow, the processing in the data processing device causes an interrupt and the subsequent handling is left to the program; in the case of lower overflow, the programmer selects whether to cause an interrupt and handle the subsequent processing by the program. , or force the result to be a true 0 without causing an interrupt and continue the operation. This method imposes a burden on the user when processing with a program, and in the case of low-order overflow, the result is set to true 0.
The disadvantage was that the accuracy deteriorated. Therefore, there is a reason why a system that can display numerical values over a wider range is desired.

Although the system shown in Fig. 2 has never been incorporated into an actual computer, it is a method shown in textbooks, etc., and was designed to be able to display a wider range of numerical values. In Figure 2, 4 is a 1-bit code, 5
is a variable-length exponent part, 6 is a variable-length mantissa part, and 7 is a display control part for specifying the length of the exponent part.
This method dynamically moves the boundary between the exponent part 5 and the mantissa part 6 depending on the value to be displayed, and for numbers that require a large exponent part, the precision of the mantissa part decreases, but this can be shortened. The effectiveness of this method has been demonstrated through simulation. However, a major drawback is that this system is completely different from the normal floating point display system currently in use as shown in FIG. 1, and that conventional programs that have been stored cannot be used at all. This is the reason why it is not actually incorporated into computers, even though its effectiveness has been shown through simulation.

Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks, use the conventional floating point representation as a basic format, and make it possible to distinguish it from the basic format when a numerical value in a range that cannot be displayed in the basic format occurs. To provide a floating point arithmetic method which allows the accumulation of conventional programs to be used as is by displaying this in a special format, and which allows the user to use it without being aware of overflow or losing precision. It is in.

General Description of the Invention In order to achieve the above object, the conventional floating point representation system is adopted as its basic format without any changes, and a special format that can be distinguished from this is adopted. It is necessary to devise a. For example, if all the bits in the part corresponding to the exponent part of the basic format are 1, it may be possible to use a special format; Since this is a permissible display, if this is excluded from the basic format, conventional programs will no longer be usable. In the present invention, numbers are normally normalized under floating point representation, and the most significant digit of the mantissa is 0.
By noting that this is not the case, and by setting the most significant digit of the part corresponding to the mantissa of the basic format to 0 in the special format, conventional programs can be used as is, and it is still possible to distinguish between the basic format and the special format. This is a method of calculating separately.

Embodiment of the Invention Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

3 and 4 show floating point display formats employed in one embodiment of the present invention.

Figure 3 shows a basic format that matches the floating point display currently used in many electronic computers, an example of which is shown in Figure 1. 1 is a 1-bit sign (bit 0), and 2 is a 7-bit sign. Exponent part (bits 1-7) with 64 remainder code, 3 consists of 56 bits
A 14-digit hexadecimal mantissa (bits 12-63), 8 is part of the mantissa 3 and is the most significant digit (4 bits) of the mantissa. Floating point representations are usually normalized to maintain precision, and the most significant digit 8 of the mantissa is usually not 0. The exception is sign 1, exponent 2, mantissa 3
A true 0 in which all bits in each part are 0.
The basic format of floating point representation in this example is:
In the format shown in FIG. 3, it refers to all bit patterns that display a true 0 and, if not a true 0, at least one bit out of the four bits of portion 8 is 1.

Figure 4 shows a special format corresponding to this basic format, where 9 consists of 4 bits that are always 0, and the tab part (bit 9) is located at the same bit position as the most significant digit 8 of the mantissa in the basic format in 8-11) to distinguish the special form from the basic form, and 10
is the 1-bit sign (bit 0), 11 is the exponent part,
12 is the most significant digit of the mantissa (bits 4-7), 13
are the remaining digits of the mantissa, and 14 is a non-number display part consisting of 3 bits. The length of the exponent part 11 is sufficiently longer than the exponent part in the basic format, so that numerical values that overflow in the upper or lower positions in the basic format can be displayed in almost all practical cases. For example, it is possible to give 20 to 32 bits to the exponent. The mantissa consists of the most significant digit 12 and the remaining digit 13. If 20 bits are given to the exponent, the mantissa becomes
Even if 9 hexadecimal digits and 32 bits are given, the result will be 6 digits, which can still maintain sufficient accuracy in many practical cases. Due to normalization, at least one bit out of the four bits of the most significant digit 12 of the mantissa is 1, so it can be distinguished from a true 0 in the basic form. Although the special format has a sufficiently long exponent part compared to the basic format, its range is finite, so even this exponent part may still cause upper or lower overflow. For these cases, the special format of this embodiment is provided with a non-number display section 14 shown in FIG. 4, so that infinity, infinitesimal, indeterminate, etc. can be displayed.

As shown in this embodiment, the present invention employs the conventional floating-point representation as its basic format, so the stored conventional programs can be used as they are without modification. be able to. When a lower overflow or an upper overflow occurs in the basic format, conventional arithmetic and control units can detect this and cause an interrupt to the currently executing program. In this embodiment, the arithmetic and control unit has a configuration as shown in FIG. 5, and instead of causing an interrupt, the signal is used to switch the result to a special format, and the result generated in this way is special format floating point representation,
A mixture of representations of the basic formats is used, and the arithmetic mechanism is switched to suit each format depending on which format is given as an operand. FIG. 5, which is an embodiment of these mechanisms, will be described below.

In FIG. 5, 15 and 16 are registers that accommodate the first and second operands, respectively, prior to the operation, and 17 and 18 detect whether the first and second operands are in the basic format or special format, respectively. circuits 19 and 20 decompose the first and second operands into a mantissa and an exponent under the control of the format detection circuits 17 and 18, respectively; 21 and 22 accommodate the mantissa and exponent of the first operand, respectively; The registers 23 and 24 contain the mantissa and exponent of the second operand, respectively, and the registers 25 and 26 contain the operations specified by the floating-point operation instruction for the mantissa and exponent decomposed in this way, respectively. circuit for applying, 27
28 is a circuit for detecting whether upper or lower overflow occurs in the basic form of the calculation result, and 28 is a circuit for synthesizing the result into one of the forms under the control of the overflow detection circuit 27.

Now, when operands are given to registers 15 and 16 when executing a floating point arithmetic instruction,
Format detection circuits 17 and 18 each detect whether a given operand is a basic format or a special format. This detection is performed by referring to the part corresponding to the most significant digit of the mantissa part of the basic format and special format. That is, bits 4-11 (third
4). If the part corresponding to the most significant digit of the mantissa in the basic form (bits 8-11) is 0, and the part corresponding to the most significant digit of the mantissa in the special form (bits 4-7) is not 0, then it is special. Detects operands of the form. Other than this case, that is, when bits 4-11 are all 0, or when bits 8-11 are not 0, the basic format is detected. The format detection circuits 17 and 18 operate the arithmetic mechanism according to the detected format. First, the detection circuits 17 and 18 are replaced by the decomposition circuits 19 and 20.
tells the detected format to . The decomposition circuits 18 and 19 decompose it into an exponent part and a mantissa part in accordance with this, and send them to registers 21, 23, 22, and 24, respectively. Of course, both the first and second operands may be in the basic form or the special form, or one may be in the basic form and the other in the special form.

The mantissa calculation circuit 25 and the exponent calculation circuit 26 perform specified calculations on the mantissas and exponents of 21, 23, 22, and 24, respectively. The digits of both operands are aligned during the operation. The result synthesis circuit 28 synthesizes the calculation results from both the calculation circuits 25 and 26 into one of the formats under the control of the overflow detection circuit 27. In the basic form, when the overflow detection circuit 27 obtains an operation result that causes an overflow, it supplies a signal to the result synthesis circuit 28 together with an indication as to whether the overflow is in the upper or lower order. The result synthesis circuit 28 switches its operation to display in the basic format when no signal is given from the overflow detection circuit 27, and to display in the special format when the signal is given. Although this result is returned to the register 15 that contained the first operand in FIG. 5, it can of course also be written to a storage device. In this way, the display in the basic format and the display in the special format are used together.

The above explanation does not mention the case where the operand is a special form and is non-numeric. In this case, the format detection circuit 17 first detects that it is a special format, and then detects that at least one bit of the three bits in the non-number display section 14 in FIG. 4 is 1,
Start processing non-numbers. The processing for non-numbers is much simpler than the example shown in FIG. 5, and is not an essential part of the present invention, so it will be omitted here.

In the above embodiment, both special format synthesis and decomposition are performed by hardware, but overflow detection and format detection are performed by hardware, and the currently running program is interrupted by the detection signal. in,
It is also possible to provide an interrupt handling program with the task of composing and/or disassembling the special configuration. Since the overflow detection circuit 27 is originally included in most modern computers,
The only new hardware that needs to be prepared is the format detection circuits 17 and 18 and an interrupt mechanism based on their signals, and most of the arithmetic units can be of the current type that handles only the basic format.

Regarding the special format, the one shown in FIG. 4 is only one example, and various modifications can be considered.
FIG. 6 shows a modified embodiment. In Figure 6, 9, 10, 11 are the same as in Figure 4, and 2
9 is the address part of the mantissa, 30 is the mantissa, 31, 32
Both are unused parts for which no purpose has been determined. In this example, in order to maintain precision by keeping the number of digits in the mantissa the same as in the basic format, the mantissa is stored in a separate word, and 2
9 houses the addos. To distinguish it from a true 0, one bit may be provided in the unused portion 31 to distinguish it, but addresses in which all bits are 0 may be excluded from the 29 addresses. Similarly, a non-number display section 31 may be provided, but a part of the mantissa address may be used to specify a non-number.

Furthermore, these examples have a basic format that matches the example shown in Figure 1 of the floating point representation currently used in many electronic computers, but the maximum number of the mantissa is Upper digit is 0
If the display is not, a special format can be created by always using the current format as the basic format and using the part corresponding to the most significant digit of the mantissa as the tag section. In addition,
In the display in Figure 1, the base number was 16, but in a display with a base of 2 and normalization, the most significant bit of the mantissa is always 1, so this bit is omitted. Although there is a display, the method of the present invention cannot be applied to this display. However, electronic computers that use this display are rare.

In addition, although floating point numbers are generally used in normalized form, some electronic computers have instructions that leave the result of an operation without being normalized, and some electronic computers allow non-normalized operands. When applying the present invention to this type of electronic computer, one way is to avoid using denormalized operation instructions, but this would make programs that already use these instructions unusable. Another method would be to change the hardware so that these instructions have the same functionality as the normalization instructions. Even if this change is made, there is no problem with the operation of most programs, and the changes to the program are limited to a few special cases.

Effects of the Invention According to the present invention, a conventional program can be used in a different format that can display a wider range of numerical values, and the user can use it without being aware of overflow or losing accuracy. .

[Brief explanation of drawings]

Figure 1 shows a floating point representation that is currently widely used, Figure 2 shows another floating point representation, and Figures 3 and 4 show floating point representations for explaining the present invention. 5 is a block diagram showing one embodiment of the present invention, and FIG. 6 is a diagram showing another floating point representation for explaining the present invention. 1 and 10... sign, 2 and 11... exponent part, 3, 12, 13... mantissa part, 8 and 12...
...Most significant digit of mantissa, 15 and 16...Operand register, 17 and 18...Format detection circuit, 19 and 20...Decomposition circuit, 21 and 2
3... Mantissa register, 22 and 24... Exponent register, 25... Mantissa calculation circuit, 26... Exponent calculation circuit, 27... Overflow detection circuit, 28... Result synthesis circuit.

Claims (1)

[Scope of Claims] 1. In a data processing device that handles numerical values in floating point representation consisting of an exponent part, a mantissa part, and a sign, all bits of the exponent part, mantissa part, and sign are 0 as a floating point representation format. A first format in which the most significant digit of the mantissa part is not 0 except for true 0, and the number of bits of the exponent part and the mantissa part are different from the first format,
and a second format in which the part corresponding to the most significant digit of the mantissa part of the first format is 0, and the most significant digit of the mantissa part is not 0, and the mantissa of the first and second formats A floating point arithmetic method that detects the display format from the part corresponding to the most significant digit of the part and operates the arithmetic mechanism accordingly. 2. The floating point arithmetic system according to claim 1, wherein one of the display formats is adopted depending on the arithmetic result in the arithmetic mechanism.