JPH04302155A - Method of screening semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a screening method, wherein in a burn-in screening of a semiconductor integrated circuit, many defectives are removed in a short time by a high application voltage and thereafter, defective devices are removed from population within a short time by the application of a voltage lower than the above high voltage. CONSTITUTION:Initial defectives are removed by a burn-in screening using a first application voltage higher than the operation guarantee power supply voltage of a semiconductor integrated circuit to be screened and moreover, a short-time burn-in screening is performed by a second application voltage, which is lower than the first application voltage and is higher than the operation guarantee supply voltage.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for screening semiconductor integrated circuits, and more particularly to burn-in screening.

0002

[Prior Art] Conventional burn-in screening involves applying a single voltage higher than the guaranteed operation power supply voltage of the semiconductor integrated circuit to be screened, and performing voltage/temperature accelerated aging in a temperature environment higher than the guaranteed operation temperature. This was done to screen for defective products.

For example, the guaranteed operation power supply voltage is 5V±10%.
If it is a semiconductor integrated circuit that has a general guaranteed operation temperature range of -10°C to 70°C, the power supply voltage is generally 6 to 8 V, and the operating temperature range is 100 to 130°C. Screening has been performed by selecting a specific temperature and applying voltage/temperature accelerated aging for several hours to several tens of hours.

[0004] FIG. 2 is a diagram showing the cumulative failure rate that appears in the conventional screening method for semiconductor integrated circuits.

As shown in FIG. 2, the operation guaranteed power supply voltage is 5.
V±10%, applied voltage 5,
Cumulative defective rate curve C when performing 5V screening
The initial failure rate (F1) with a cumulative failure rate of 6% converged in 70 hours, and the cumulative failure rate curve D when screening was performed at a temperature of 120°C and an applied voltage of 8.0V showed a cumulative failure rate of 6% in 10 hours. Convergence of the initial failure rate (F2) of 16% is observed.

[0006]

[Problems to be Solved by the Invention] In this conventional screening method for semiconductor integrated circuits, screening is performed using a single applied voltage (burn-in voltage), so if the burn-in voltage is too low, initial defects may occur. If removal takes a long time and the burn-in voltage is too high,
Initial defects are removed in a short time, but after screening is completed, individuals that become defective within a relatively short period of time due to a power supply voltage lower than the burn-in voltage may remain in the mother body.

[0007] For this reason, if the burn-in voltage is kept low, the time required for screening will be long and productivity will be significantly reduced, and if the burn-in voltage is set high, there is a risk of degrading the quality at the time of shipment. There was a problem.

[0008]

Means for Solving the Problems A semiconductor integrated circuit screening method of the present invention includes applying a first voltage higher than the operation guaranteed power supply voltage of the semiconductor integrated circuit to the semiconductor integrated circuit to perform first burn-in screening. and a step of applying a second voltage lower than the first voltage and higher than the operation guaranteed power supply voltage to the semiconductor integrated circuit to perform a second burn-in screening. Consists of.

[0009]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the cumulative defect rate that appears according to an embodiment of the present invention.

First, for a semiconductor integrated circuit having the same guaranteed operating voltage and guaranteed operating temperature range as the conventional example,
The burn-in was carried out until the time t1 (10 hours in this example) at which most of the initial defects in the burn-in screening were removed at 20° C. and the applied burn-in voltage was set to 8 V (the cumulative failure rate curve A was saturated). Then, set the burn-in voltage to 5.5V and continue the burn-in until time t2 (in this example, the time from time t1 to time t2 is 4 hours).In this case, the theoretical The probability of defect occurrence is as shown by curve B, and the probability of defect occurrence should become almost 0 from time t1 when the burn-in voltage is lowered, but in reality, defects continue to occur for a while after time t1.
Afterwards, the defect occurrence probability becomes almost 0, similar to the theoretical value.

This is because defect screening by 8V burn-in microscopically adds stress to defects that can be removed in a short time only by 8V burn-in (defects that lead to defects between F1 and F2 in FIG. 2). ,《5.5V
Defects that can be removed in a relatively short time by burn-in (
It consists of two processes: a process of changing the defect to a defect that leads to a defect at F1 or below in Figure 2), and a process of adding stress to the defect, which can be removed in a relatively short time even by 5.5V burn-in, and causing it to fail. It is assumed that
This is thought to be because if the 8V burn-in is stopped at a certain point, solids with "defects that can be removed in a relatively short time even by 5.5V burn-in" will remain in the matrix with a certain probability.

In the conventional screening method, when burn-in was performed at 5.5V for 10 hours for quality confirmation after the screening was completed, the semiconductor integrated circuit had a failure rate of about 1%, but the screening method according to the present invention has a defect rate of about 1%. In a similar quality check after completion of screening, it was confirmed that the defect rate was improved to approximately 0.1%.

[0014] In addition, when screening was performed using the screening method of the present invention, similar quality confirmation was achieved for other varieties, for which the defect rate was approximately 0.2% in the same quality confirmation after completion of conventional screening. It was also confirmed that the defect rate was improved to about 0.04%.

[0015]

Effects of the Invention As explained above, according to the present invention, since the quality confirmation result by the 5.5V, 10-hour burn-in screening described above is considered to correspond to the quality at the time of delivery of the semiconductor integrated circuit, it is possible to prevent defects from being mixed in at the time of delivery. Rate 10,00
A product with a defective contamination rate of 0 ppm becomes 1,000 ppm, and a product with a defective contamination rate of 2,000 ppm becomes 400 ppm, which has the effect of realizing a significant quality improvement.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the cumulative defective rate that appears according to an embodiment of the present invention.

FIG. 2 is a diagram showing the cumulative defective rate that appears in a conventional screening method for semiconductor integrated circuits.

Claims (1)

[Claims] 1. A step of applying a first voltage higher than a guaranteed operation power supply voltage of the semiconductor integrated circuit to the semiconductor integrated circuit to perform a first burn-in screening to remove initial defects; 1. A method for screening a semiconductor integrated circuit, comprising the step of performing a second burn-in screening by applying a second voltage to the semiconductor integrated circuit that is lower than the operation-guaranteed power supply voltage and higher than the operation-guaranteed power supply voltage.