JPH043040B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a latch circuit using Josephson junctions, more specifically, a dual rail system in which a true signal and a complementary signal are input into the circuit, and further input. This relates to a latch circuit that temporarily stores information in a logic circuit.

(Prior Art) Once a Josephson junction element is switched to a voltage state, it performs a latching operation in which the voltage state is maintained unless the power supply current is cut off. For this reason,
In logic circuits using Josephson junctions, an AC power supply system in which the power supply current is reset to 0 once is common. In this power supply system, a latch circuit that holds the calculated results while the power supply current is 0 is essential. On the other hand, it is more difficult to construct an inverter in logic circuits using Josephson junctions than in semiconductors, and a dual rail system is generally adopted. The dual rail method is a circuit method in which the complementary signal of the input signal is simultaneously input into the logic circuit, and the complementary signal of the output signal is also generated simultaneously in the logic circuit, and it uses an inverter that requires a timing signal. Since this is not necessary, the speed of the circuit can be increased. Therefore, there is a need for a dual rail type latch circuit in which both the true signal and the complementary signal are outputted from the above-mentioned latch circuit.

Several latch circuits have been proposed and researched in the past, and here we will discuss a conventional example shown in FIG. 4, which is superior in terms of the circuit area it occupies. The operation of this conventional latch circuit is described in the literature Journal of Applied Physics vol.59(9).
Since I am familiar with pp3196-3201, I will only briefly describe it here. FIG. 4 shows an equivalent circuit of a conventional example, in which 40 is a data input line, 41 is a latch enable signal line, 42, 43, 44, 4
7 and 48 are Josephson junctions, 45 is an inductance, 46 is a sense signal input line, 49,400,
401 is a resistor, 402 is an auxiliary signal output line, 403
is the true signal output line, and Josephson junction 42
and an inductance 45 constitute a data holding loop. When writing data "1", a data signal and a latch enable signal are input to the data holding loop through a data input line and a latch enable signal line. This results in Josephson junction 42
switches and stores the data in a data retention loop as a persistent current. The latch enable signal is used to notify the timing of writing to the latch circuit and to reset the data in the data retention loop. Since the latch circuit is used in bipolar AC driving, a latch enable signal having a polarity different from the input signal input to the data holding loop during the previous machine cycle is input to the next stage. Therefore, the persistent current flowing in the data retention loop and the latch enable signal are connected to Josephson junction 42.
This Josephson junction 42 switches and resets the persistent current. Reading is performed when the sense gate current flowing through the sense signal input line 46 rises. When a persistent current flows in the data retention loop, Josephson junction 43,
44 switches, and an output appears on the true signal output line 403. If no persistent current flows in the data retention loop, the critical current value of the Josephson junction 47 is exceeded at the final stage when the sense gate current rises, and the Josephson junction 47 switches, followed by the Josephson junction 48, and the auxiliary signal is switched. An output appears on output line 402. In the manner described above, a Josephson latch circuit can be realized.

(Problems to be Solved by the Invention) However, the above-described latch circuit has the following problems. That is, when resetting data, a gate current with a polarity different from that of the previous machine cycle is always required. In other words, it can only be used in bipolar AC powered systems. It goes without saying that Josephson integrated circuits require not only logic circuits but also memory circuits. Josephson memory circuits are difficult to operate with bipolar AC drive, as information is attached to the polarity of the current or operates by superimposing currents.
Therefore, other driving methods include DC drive or unipolar AC drive, but considering that the logic circuit must also be driven.
It is considered difficult to operate with DC drive.
Therefore, a unipolar AC drive system was thought to be optimal, but in that case, as mentioned above, the conventional latch circuit cannot be used.

(Means for Solving the Problems) According to the present invention, the data retention loop includes a single or multiple Josephson junctions and a superconducting inductance, and has a true signal input line and an auxiliary signal input line, one of which includes a true signal input line and an auxiliary signal input line. is connected directly to the data retention loop, the other is magnetically coupled to a portion of the data retention loop, and has a sense circuit magnetically coupled to the portion of the data retention loop; It has an output circuit that reads the information held in the data holding loop and generates a true signal and a complementary signal, and a signal obtained by multiplying the true signal and the latch enable signal is input to one of the two input lines. A Josephson latch circuit is obtained in which a signal obtained by multiplying the complementary signal and the latch enable signal is inputted to the other end.

(Operation) In the data holding loop of the present invention, data is written by a switch of the Josephson junction, which is composed of a Josephson junction and an inductance. When the data is "1", a true signal is input so as to exceed the critical current value of the Josephson junction, and a persistent current is written. Further, when the data is "0", the complementary signal is input so as to exceed the critical current value of the Josephson junction superimposed on the persistent current, and the persistent current is reset. Since each input signal is input after performing a product operation with the latch enable signal, there is no problem with the timing of inputting the input signal. The data held in the data holding loop is read by a sense gate circuit magnetically coupled to the data holding loop, and a true signal and a complementary signal are output.

(Embodiment) FIGS. 1 to 3 are diagrams for explaining an embodiment of the present invention, and FIG. 1 shows an equivalent circuit of the embodiment. In the figure, 1 is a true signal input line, and 2 is a complementary signal input line. Input lines, 3, 8, 19 are Josephson junctions, 4, 5,
6 is an inductance, 7 is an interferometer gate circuit, 9 is a gate current line, 10 and 11 are output resistors, 12 is a true signal output line, 13 is an auxiliary signal output line, 14 is a latch enable signal line, 1
5 and 16 are product calculation circuits, 17 is a true signal line, and 18 is a complementary signal line. Assuming that the phase difference of the order parameters of Josephson junction 3 is θ, the current-phase characteristics with respect to the current _Ie input from true signal input line 1 are as shown in FIG. In Figure 2, 2
1 to 26 each indicate an operating point. This current-phase characteristic is determined by the critical current value of Josephson junction 3 and the inductance values of inductances 4, 5, and 6, and can be set to have the characteristics as shown in the figure. Figure 3 is an example of the gate current I _g waveform of Josephson logic circuit, which is unipolar.
This diagram schematically shows the case of AC drive, where 31 is an operating area, 32 is a data writing area, 33 is a data holding area, 34 is a machine cycle, and 35 is a data reading area.

The results calculated in the operating region 31 shown in FIG. 3 are input to the product calculation circuit 16 or 15 through the true signal line 17 or the complementary signal line 18. The latch enable signal is input to the product calculation circuits 15 and 16 and entered into the data write area 32, and data is input to the data holding loop via the true signal input line 1 or the auxiliary signal input line 2. If the calculation result is "1", a true signal is input and Josephson junction 3 is switched. That is, in FIG. 2, the operating point passes through 21 and moves to 22. After the gate current falls, the operating point moves to 23, and data is held during the data holding area 33. on the other hand,
If the calculation result is "0", the complementary signal is input.
Since the current induced in the data retention loop by the complementary signal is in the opposite direction to the true signal at Josephson junction 3, the operating point moves from 23 to 26 through 24 and 25, resetting the persistent current in the data retention loop. do. Next, at the time of reading, a gate current is applied to the interferometer gate circuit 7 through the gate current line between the data reading regions 35. When a persistent current flows in the data holding loop, this interferometer gate circuit 7 is switched on, data is read out, and a signal appears on the true signal output line. At this time, the gate current is also shunted to the resistor 10, but the resistors 10 and 11 can be appropriately selected so that this shunted current does not switch the Josephson junction 19. When no persistent current flows in the data retention loop, Josephson junction 8 switches at the final stage of the rise of the gate current, followed by Josephson junction 19, and an output signal appears on the auxiliary signal output line. At this time, since no gate current flows to the interferometa gate circuit 7 in the operating region, even if the state of the data holding loop changes, the output is not affected.

As described above, a Josephson latch circuit can be realized using this circuit. This circuit is a latch circuit that uses a dual rail system, and is a latch circuit that is used when using a unipolar AC drive system. As outputs, a true signal and a complementary signal are generated.

(Effects of the Invention) The latch circuit of the present invention can be used in a unipolar AC drive system and does not require any timing sequence for its operation. Furthermore, since a single Josephson junction is used for writing data, the area occupied by the circuit can be reduced.

[Brief explanation of drawings]

1, 2, and 3 are diagrams for explaining an embodiment of the present invention. FIG. 1 is an equivalent circuit diagram of the embodiment, and FIG. 2 is a current-phase characteristic diagram of a data retention loop. Figure 3 is a gate current waveform diagram of the unipolar AC drive system. FIG. 4 is an equivalent circuit diagram of a conventional example. The numbers in the figure are 1... true signal input line, 2... auxiliary signal input line, 3, 8, 19... Josephson junction, 4, 5, 6... inductance, 7... interferometer gate circuit. ,9
...gate current line, 10,11...output resistance,
12...True signal output line, 13...Auxiliary signal output line, 14...Latch enable signal line, 15,1
6... Product calculation circuit, 17... True signal line, 18...
Auxiliary signal line, 21, 22, 23, 24, 25, 26
...Operating point, 31...Operating area, 32...Data writing area, 33...Data holding area, 34...
...Machine cycle, 35...Data read area, 40...Data input line, 41...Latch enable signal line, 42, 43, 44, 47, 48...
... Josephson junction, 45... inductance,
46...Sense signal input line, 49,400,40
1... Resistor, 402... Auxiliary signal output line, 403
...Indicates the true signal output line.

Claims (1)

[Claims] 1. It has a data retention loop consisting of a single or multiple Josephson junctions and superconducting inductances, and has a true signal input line and an auxiliary signal input line, one of which is directly connected to the data retention loop, and the other is directly connected to the data retention loop. A sense circuit is magnetically coupled to a portion of the data retention loop, and a sense circuit is magnetically coupled to a portion of the data retention loop, and the sense circuit reads information retained in the data retention loop and determines a true signal. It has an output circuit that generates a complementary signal, and one of the two input lines mentioned above receives a signal obtained by multiplying the true signal and the latch enable signal, and the other receives a signal obtained by multiplying the complementary signal and the latch enable signal. A Josephson latch circuit characterized by a signal input.